The SpiNNaker Project

The spiking neural network architecture (SpiNNaker) project aims to deliver a massively parallel million-core computer whose interconnect architecture is inspired by the connectivity characteristics of the mammalian brain, and which is suited to the modeling of large-scale spiking neural networks in...

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Veröffentlicht in:Proceedings of the IEEE Jg. 102; H. 5; S. 652 - 665
Hauptverfasser: Furber, Steve B., Galluppi, Francesco, Temple, Steve, Plana, Luis A.
Format: Journal Article
Sprache:Englisch
Veröffentlicht: New York IEEE 01.05.2014
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Schlagworte:
Architecture (computers)
Brain
Brain modeling
Computational modeling
Computer architecture
Interconnections
multicast algorithms
multiprocessor interconnection networks
Multitasking
neural network hardware
Neural networks
Neuroscience
Packet transmission
Parallel programming
Program processors
Programming
Real time
Spiking
Brain modeling
multicast algorithms
neural network hardware
multiprocessor interconnection networks
parallel programming
ISSN:0018-9219, 1558-2256
Online-Zugang:Volltext
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Zusammenfassung:The spiking neural network architecture (SpiNNaker) project aims to deliver a massively parallel million-core computer whose interconnect architecture is inspired by the connectivity characteristics of the mammalian brain, and which is suited to the modeling of large-scale spiking neural networks in biological real time. Specifically, the interconnect allows the transmission of a very large number of very small data packets, each conveying explicitly the source, and implicitly the time, of a single neural action potential or "spike." In this paper, we review the current state of the project, which has already delivered systems with up to 2500 processors, and present the real-time event-driven programming model that supports flexible access to the resources of the machine and has enabled its use by a wide range of collaborators around the world.
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ISSN:0018-9219
1558-2256
DOI:10.1109/JPROC.2014.2304638