FPGA implementation of low complexity LDPC iterative decoder

Low-density parity-check (LDPC) codes, proposed by Gallager, emerged as a class of codes which can yield very good performance on the additive white Gaussian noise channel as well as on the binary symmetric channel. LDPC codes have gained lots of importance due to their capacity achieving property a...

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Veröffentlicht in:International journal of electronics Jg. 103; H. 7; S. 1112 - 1126
Hauptverfasser: Verma, Shivani, Sharma, Sanjay
Format: Journal Article
Sprache:Englisch
Veröffentlicht: Abingdon Taylor & Francis 02.07.2016
Taylor & Francis LLC
Schlagworte:
Algorithms
Architecture
Channels
check-node unit
Codes
Complexity
Decoders
Decoding
Electrical engineering
Error correcting codes
iterative decoding algorithms
LDPC
Message passing
parity-check matrix
Propagation
SMPA
ISSN:0020-7217, 1362-3060
Online-Zugang:Volltext
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Zusammenfassung:Low-density parity-check (LDPC) codes, proposed by Gallager, emerged as a class of codes which can yield very good performance on the additive white Gaussian noise channel as well as on the binary symmetric channel. LDPC codes have gained lots of importance due to their capacity achieving property and excellent performance in the noisy channel. Belief propagation (BP) algorithm and its approximations, most notably min-sum, are popular iterative decoding algorithms used for LDPC and turbo codes. The trade-off between the hardware complexity and the decoding throughput is a critical factor in the implementation of the practical decoder. This article presents introduction to LDPC codes and its various decoding algorithms followed by realisation of LDPC decoder by using simplified message passing algorithm and partially parallel decoder architecture. Simplified message passing algorithm has been proposed for trade-off between low decoding complexity and decoder performance. It greatly reduces the routing and check node complexity of the decoder. Partially parallel decoder architecture possesses high speed and reduced complexity. The improved design of the decoder possesses a maximum symbol throughput of 92.95 Mbps and a maximum of 18 decoding iterations. The article presents implementation of 9216 bits, rate-1/2, (3, 6) LDPC decoder on Xilinx XC3D3400A device from Spartan-3A DSP family.
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ISSN:0020-7217
1362-3060
DOI:10.1080/00207217.2015.1087052