APA-Zitierstil (7. Ausg.)

Verma, S., & Sharma, S. (2016). FPGA implementation of low complexity LDPC iterative decoder. International journal of electronics, 103(7), 1112-1126. https://doi.org/10.1080/00207217.2015.1087052

Chicago-Zitierstil (17. Ausg.)

Verma, Shivani, und Sanjay Sharma. "FPGA Implementation of Low Complexity LDPC Iterative Decoder." International Journal of Electronics 103, no. 7 (2016): 1112-1126. https://doi.org/10.1080/00207217.2015.1087052.

MLA-Zitierstil (9. Ausg.)

Verma, Shivani, und Sanjay Sharma. "FPGA Implementation of Low Complexity LDPC Iterative Decoder." International Journal of Electronics, vol. 103, no. 7, 2016, pp. 1112-1126, https://doi.org/10.1080/00207217.2015.1087052.