ONOFIC approach: low power high speed nanoscale VLSI circuits design

Shrinking in the device dimensions increases the device density on the chip and thus reducing the overall chip area requirement for logic implementation. Minimising the chip area is not a lonely optimisation performance factor for a VLSI chip designer. The other equally important performance paramet...

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Bibliographic Details

Published in:	International journal of electronics Vol. 101; no. 1; pp. 61 - 73
Main Authors:	Sharma, V.K., Pattanaik, M., Raj, B.
Format:	Journal Article
Language:	English
Published:	Abingdon Taylor & Francis 02.01.2014 Taylor & Francis LLC
Subjects:	Chips Circuits Design engineering Electrical engineering High speed leakage Current LECTOR nanoscale CMOS ONOFIC PDP
ISSN:	0020-7217, 1362-3060
Online Access:	Get full text
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