A sigma–delta analog to digital converter based on iterative algorithm

In this article, we present a new iterative algorithm aimed at improving the performance of the sigma–delta analog to digital (A/D) converter. We subject the existing sigma–delta modulator, without changing the configuration, to an iterative procedure to increase the signal-to-noise ratio of the rec...

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Vydáno v:EURASIP journal on advances in signal processing Ročník 2012; číslo 1; s. 1 - 7
Hlavní autoři: Kafashan, Mohammadmehdi, Ghorbani, Mahboobeh, Marvasti, Farokh
Médium: Journal Article
Jazyk:angličtina
Vydáno: Cham Springer International Publishing 18.07.2012
Témata:
Analog to digital converters
Boards
Computer simulation
Converters
Engineering
Field programmable gate arrays
Hardware
Iterative algorithms
Modulators
Quantum Information Technology
Signal,Image and Speech Processing
Spintronics
Reconstructed Signal
Quantization Noise
Iterative Algorithm
Distorted Version
Inverse System
ISSN:1687-6180, 1687-6172, 1687-6180
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Shrnutí:In this article, we present a new iterative algorithm aimed at improving the performance of the sigma–delta analog to digital (A/D) converter. We subject the existing sigma–delta modulator, without changing the configuration, to an iterative procedure to increase the signal-to-noise ratio of the reconstructed signal. In other words, we demonstrate that sigma–delta modulated signals can be decoded using the iterative algorithm. Simulation results confirm that the proposed method works very well, even when less complex filters are used. The simple and regular structure of this new A/D converter, not only makes realization of the hardware as ASIC or on FPGA boards easy, but also allows it to operate at high frequency levels with optimized power consumption and small chip area. Implementation of the design with an FPGA shows that experimental results are in agreement with the simulation results.
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ISSN:1687-6180
1687-6172
1687-6180
DOI:10.1186/1687-6180-2012-149