Field programmable gate array implementation of variable-bins high efficiency video coding CABAC decoder with path delay optimisation
Context-based adaptive binary arithmetic coding (CABAC) is a single operation mode for entropy coding in the last video coding standard high-efficiency video coding. For high-resolution applications, the throughput of one bin/cycle is not sufficient and it is a very challenging task to implement pip...
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| Vydáno v: | IET image processing Ročník 13; číslo 6; s. 954 - 963 |
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| Médium: | Journal Article |
| Jazyk: | angličtina |
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The Institution of Engineering and Technology
01.05.2019
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| ISSN: | 1751-9659, 1751-9667 |
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| Abstract | Context-based adaptive binary arithmetic coding (CABAC) is a single operation mode for entropy coding in the last video coding standard high-efficiency video coding. For high-resolution applications, the throughput of one bin/cycle is not sufficient and it is a very challenging task to implement pipeline and/or parallel CABAC decoding architecture by simply adding more stages. Indeed, the tight data dependencies make it difficult to parallelise and cause it to be a throughput bottleneck for video decoding. Consequently, in order to improve the CABAC decoder throughput, parallel and pipeline architectures are used in authors’ design. In this work, an algorithm-architecture adequation is proposed to implement a CABAC decoder on a field programmable gate array. Mainly, a new classification of 32 syntax elements is given to speed up the authors’ solution. Furthermore, the context selection and modelling of regular syntax elements are studied, designed and implemented. Finally, a novel technique of memories rearrangement to reduce the critical path delay required to process each binary symbol is proposed. As a result, the implementation can process 2.2 bins/cycle when operated at 123.49 MHz and exhibits an improved high-throughput of 271.678 Mbins/s. The hardware architecture is coded using hardware description language and synthesised using ISE Xilinx tools targeting the Virtex4 platform. |
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| AbstractList | Context‐based adaptive binary arithmetic coding (CABAC) is a single operation mode for entropy coding in the last video coding standard high‐efficiency video coding. For high‐resolution applications, the throughput of one bin/cycle is not sufficient and it is a very challenging task to implement pipeline and/or parallel CABAC decoding architecture by simply adding more stages. Indeed, the tight data dependencies make it difficult to parallelise and cause it to be a throughput bottleneck for video decoding. Consequently, in order to improve the CABAC decoder throughput, parallel and pipeline architectures are used in authors’ design. In this work, an algorithm‐architecture adequation is proposed to implement a CABAC decoder on a field programmable gate array. Mainly, a new classification of 32 syntax elements is given to speed up the authors’ solution. Furthermore, the context selection and modelling of regular syntax elements are studied, designed and implemented. Finally, a novel technique of memories rearrangement to reduce the critical path delay required to process each binary symbol is proposed. As a result, the implementation can process 2.2 bins/cycle when operated at 123.49 MHz and exhibits an improved high‐throughput of 271.678 Mbins/s. The hardware architecture is coded using hardware description language and synthesised using ISE Xilinx tools targeting the Virtex4 platform. |
| Author | Belhadj, Aichouche Skoudarli, Abdellah Menasri, Wahiba Azzaz, Mohamed Salah |
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| Cites_doi | 10.1117/12.953686 10.1109/TCAD.2006.884574 10.1109/ISCAS.2010.5537137 10.1109/TCSVT.2012.2221526 10.1049/el:20082126 10.1109/MCE.2012.2192754 10.1117/12.593980 10.1109/ISCE.2014.6884467 10.1109/TCSVT.2009.2020326 10.1080/13682199.2018.1477486 10.1109/TVLSI.2008.2005286 10.1109/FPT.2006.270301 10.1109/MMUL.2017.12 10.1007/s11265-012-0718-y 10.4028/www.scientific.net/AMM.340.685 10.1109/TCSVT.2012.2221191 10.1109/TCSVT.2014.2363748 10.1109/HDP.2007.4283645 10.1109/TCE.2006.1649684 10.1109/ICSES.2012.6382256 10.1109/JSSC.2011.2169310 10.1109/TCSVT.2009.2020340 |
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| Keywords | field programmable gate array implementation CABAC decoding architecture algorithm-architecture adequation field programmable gate arrays bin/cycle video coding standard high-efficiency video coding hardware description languages throughput bottleneck arithmetic codes path delay optimisation critical path delay high-throughput context-based adaptive binary arithmetic coding CABAC decoder throughput frequency 123.49 MHz binary codes entropy coding entropy codes single operation mode video coding adaptive codes 2.2 bins/cycle decoding high-resolution applications video decoding variable-bins high efficiency video coding CABAC decoder pipeline architectures |
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| SubjectTerms | 2.2 bins/cycle adaptive codes algorithm‐architecture adequation arithmetic codes bin/cycle binary codes CABAC decoder throughput CABAC decoding architecture context‐based adaptive binary arithmetic coding critical path delay decoding entropy codes entropy coding field programmable gate array implementation field programmable gate arrays frequency 123.49 MHz hardware description languages high‐resolution applications high‐throughput path delay optimisation pipeline architectures Research Article single operation mode throughput bottleneck variable‐bins high efficiency video coding CABAC decoder video coding video coding standard high‐efficiency video coding video decoding |
| Title | Field programmable gate array implementation of variable-bins high efficiency video coding CABAC decoder with path delay optimisation |
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