Minimizing communication in the bitonic sort

This paper presents bitonic sorting schemes for special-purpose parallel architectures such as sorting networks and for general-purpose parallel architectures such as SIMD and/or MIMD computers. First, bitonic sorting algorithms for shared-memory SIMD and/or MIMD computers are developed. Shared-memo...

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Veröffentlicht in:IEEE transactions on parallel and distributed systems Jg. 11; H. 5; S. 459 - 474
Hauptverfasser: Jae-Dong Lee, Batcher, K.E.
Format: Journal Article
Sprache:Englisch
Veröffentlicht: New York IEEE 01.05.2000
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Schlagworte:
Communication switching
Computer networks
Concurrent computing
Cost engineering
Costs
Interconnection
Multiprocessor interconnection networks
Networks
Parallel architectures
Parity
Sorting
Strategy
Studies
Switches
Switching theory
Time sharing computer systems
Wiring
ISSN:1045-9219, 1558-2183
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Zusammenfassung:This paper presents bitonic sorting schemes for special-purpose parallel architectures such as sorting networks and for general-purpose parallel architectures such as SIMD and/or MIMD computers. First, bitonic sorting algorithms for shared-memory SIMD and/or MIMD computers are developed. Shared-memory accesses through the interconnection network of shared memory SIMD and/or MIMD computers can be very time consuming. A scheme is introduced which reduces the number of such accesses. This scheme is based on the parity strategy which is the main idea of the paper. By reducing the communication through the network, a performance improvement is achieved. Second, a recirculating bitonic sorting network is presented, which is composed of one level of N/2 comparators plus an /spl Omega/-network of (log N-1) switch levels. This network reduces the cost complexity to O(N log N) compared with the O(N log/sup 2/ N) of the original bitonic sorting network, while preserving the same time complexity. Finally, a simplified multistage bitonic sorting network, is presented. For simplifying the interlevel wiring, the parity strategy is used, so N/2 keys are wired straight through the network.
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ISSN:1045-9219
1558-2183
DOI:10.1109/71.852399