Minimizing communication in the bitonic sort

This paper presents bitonic sorting schemes for special-purpose parallel architectures such as sorting networks and for general-purpose parallel architectures such as SIMD and/or MIMD computers. First, bitonic sorting algorithms for shared-memory SIMD and/or MIMD computers are developed. Shared-memo...

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Bibliographic Details
Published in:	IEEE transactions on parallel and distributed systems Vol. 11; no. 5; pp. 459 - 474
Main Authors:	Jae-Dong Lee, Batcher, K.E.
Format:	Journal Article
Language:	English
Published:	New York IEEE 01.05.2000 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:	Communication switching Computer networks Concurrent computing Cost engineering Costs Interconnection Multiprocessor interconnection networks Networks Parallel architectures Parity Sorting Strategy Studies Switches Switching theory Time sharing computer systems Wiring
ISSN:	1045-9219, 1558-2183
Online Access:	Get full text
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