Minimizing communication in the bitonic sort

This paper presents bitonic sorting schemes for special-purpose parallel architectures such as sorting networks and for general-purpose parallel architectures such as SIMD and/or MIMD computers. First, bitonic sorting algorithms for shared-memory SIMD and/or MIMD computers are developed. Shared-memo...

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Veröffentlicht in:	IEEE transactions on parallel and distributed systems Jg. 11; H. 5; S. 459 - 474
Hauptverfasser:	Jae-Dong Lee, Batcher, K.E.
Format:	Journal Article
Sprache:	Englisch
Veröffentlicht:	New York IEEE 01.05.2000 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Schlagworte:	Communication switching Computer networks Concurrent computing Cost engineering Costs Interconnection Multiprocessor interconnection networks Networks Parallel architectures Parity Sorting Strategy Studies Switches Switching theory Time sharing computer systems Wiring
ISSN:	1045-9219, 1558-2183
Online-Zugang:	Volltext
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