Minimizing communication in the bitonic sort
This paper presents bitonic sorting schemes for special-purpose parallel architectures such as sorting networks and for general-purpose parallel architectures such as SIMD and/or MIMD computers. First, bitonic sorting algorithms for shared-memory SIMD and/or MIMD computers are developed. Shared-memo...
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| Vydáno v: | IEEE transactions on parallel and distributed systems Ročník 11; číslo 5; s. 459 - 474 |
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| Hlavní autoři: | , |
| Médium: | Journal Article |
| Jazyk: | angličtina |
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New York
IEEE
01.05.2000
The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
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| ISSN: | 1045-9219, 1558-2183 |
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| Abstract | This paper presents bitonic sorting schemes for special-purpose parallel architectures such as sorting networks and for general-purpose parallel architectures such as SIMD and/or MIMD computers. First, bitonic sorting algorithms for shared-memory SIMD and/or MIMD computers are developed. Shared-memory accesses through the interconnection network of shared memory SIMD and/or MIMD computers can be very time consuming. A scheme is introduced which reduces the number of such accesses. This scheme is based on the parity strategy which is the main idea of the paper. By reducing the communication through the network, a performance improvement is achieved. Second, a recirculating bitonic sorting network is presented, which is composed of one level of N/2 comparators plus an /spl Omega/-network of (log N-1) switch levels. This network reduces the cost complexity to O(N log N) compared with the O(N log/sup 2/ N) of the original bitonic sorting network, while preserving the same time complexity. Finally, a simplified multistage bitonic sorting network, is presented. For simplifying the interlevel wiring, the parity strategy is used, so N/2 keys are wired straight through the network. |
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| AbstractList | [...] a recirculating bitonic sorting network is presented, which is composed of one level of N/2 comparators plus an Ω-network of (log N-1) switch levels. This paper presents bitonic sorting schemes for special-purpose parallel architectures such as sorting networks and for general-purpose parallel architectures such as SIMD and/or MIMD computers. First, bitonic sorting algorithms for shared-memory SIMD and/or MIMD computers are developed. Shared-memory accesses through the interconnection network of shared memory SIMD and/or MIMD computers can be very time consuming. A scheme is introduced which reduces the number of such accesses. This scheme is based on the parity strategy which is the main idea of the paper. By reducing the communication through the network, a performance improvement is achieved. Second, a recirculating bitonic sorting network is presented, which is composed of one level of N/2 comparators plus an Omega -network of (log N - 1) switch levels. This network reduces the cost complexity to O(N log N) compared with the O(N log super(2) N) of the original bitonic sorting network, while preserving the same time complexity. Finally, a simplified multistage bitonic sorting network, is presented. For simplifying the interlevel wiring, the parity strategy is used, so N/2 keys are wired straight through the network. This paper presents bitonic sorting schemes for special-purpose parallel architectures such as sorting networks and for general-purpose parallel architectures such as SIMD and/or MIMD computers. First, bitonic sorting algorithms for shared-memory SIMD and/or MIMD computers are developed. Shared-memory accesses through the interconnection network of shared memory SIMD and/or MIMD computers can be very time consuming. A scheme is introduced which reduces the number of such accesses. This scheme is based on the parity strategy which is the main idea of the paper. By reducing the communication through the network, a performance improvement is achieved. Second, a recirculating bitonic sorting network is presented, which is composed of one level of N/2 comparators plus an Omega -network of (log N-1) switch levels. This network reduces the cost complexity to O(N log N) compared with the O(N log super(2) N) of the original bitonic sorting network, while preserving the same time complexity. Finally, a simplified multistage bitonic sorting network, is presented. For simplifying the interlevel wiring, the parity strategy is used, so N/2 keys are wired straight through the network This paper presents bitonic sorting schemes for special-purpose parallel architectures such as sorting networks and for general-purpose parallel architectures such as SIMD and/or MIMD computers. First, bitonic sorting algorithms for shared-memory SIMD and/or MIMD computers are developed. Shared-memory accesses through the interconnection network of shared memory SIMD and/or MIMD computers can be very time consuming. A scheme is introduced which reduces the number of such accesses. This scheme is based on the parity strategy which is the main idea of the paper. By reducing the communication through the network, a performance improvement is achieved. Second, a recirculating bitonic sorting network is presented, which is composed of one level of N/2 comparators plus an Omicron-network of (log N-1) switch levels. This network reduces the cost complexity to O(N log N) compared with the O(N log(2) N) of the original bitonic sorting network, while preserving the same time complexity. Finally, a simplified multistage bitonic sorting network, is presented. For simplifying the interlevel wiring, the parity strategy is used, so N/2 keys are wired straight through the network This paper presents bitonic sorting schemes for special-purpose parallel architectures such as sorting networks and for general-purpose parallel architectures such as SIMD and/or MIMD computers. First, bitonic sorting algorithms for shared-memory SIMD and/or MIMD computers are developed. Shared-memory accesses through the interconnection network of shared memory SIMD and/or MIMD computers can be very time consuming. A scheme is introduced which reduces the number of such accesses. This scheme is based on the parity strategy which is the main idea of the paper. By reducing the communication through the network, a performance improvement is achieved. Second, a recirculating bitonic sorting network is presented, which is composed of one level of N/2 comparators plus an /spl Omega/-network of (log N-1) switch levels. This network reduces the cost complexity to O(N log N) compared with the O(N log/sup 2/ N) of the original bitonic sorting network, while preserving the same time complexity. Finally, a simplified multistage bitonic sorting network, is presented. For simplifying the interlevel wiring, the parity strategy is used, so N/2 keys are wired straight through the network. |
| Author | Jae-Dong Lee Batcher, K.E. |
| Author_xml | – sequence: 1 surname: Jae-Dong Lee fullname: Jae-Dong Lee organization: Dept. of Comput. Sci., Dankook Univ., South Korea – sequence: 2 givenname: K.E. surname: Batcher fullname: Batcher, K.E. |
| BookMark | eNqF0TtPwzAQAGALFYm2MLAyRQwgJNL6_Io9ooqXVMQCc-QkDrhq7BInA_x6DKkYKgTTWefvfDrfBI2cdwahY8AzAKzmGcwkJ1SpPTQGzmVKQNJRPGPGU0VAHaBJCCuMgXHMxujywTrb2A_rXpLSN03vbKk7611iXdK9mqSwnY-5JPi2O0T7tV4Hc7SNU_R8c_20uEuXj7f3i6tlWlKRdSnXGY3tJCWaVFAAqxiISpmC8qrCosaE1qzUkUlWMyZkgUELQWRRQc2xolN0Pry7af1bb0KXNzaUZr3Wzvg-5AqYoMAIj_LsT0kklYLy7H-YCUypEBGe7sCV71sXx80VwUIwInFE8wGVrQ-hNXVe2u7727pW23UOOP_aRp5BPmwjVlzsVGxa2-j2_Vd7MlhrjPlx28tPzsiQyw |
| CODEN | ITDSEO |
| CitedBy_id | crossref_primary_10_1109_TCSI_2022_3204645 crossref_primary_10_1016_j_jpdc_2013_09_008 crossref_primary_10_1109_TPDS_2015_2475763 crossref_primary_10_1109_TC_2012_108 crossref_primary_10_1016_j_jbiomech_2017_10_023 crossref_primary_10_1006_jpdc_2001_1808 crossref_primary_10_1145_3391443 crossref_primary_10_1016_S0167_739X_01_00056_5 crossref_primary_10_1109_TPDS_2017_2705128 crossref_primary_10_1109_TIE_2021_3104600 crossref_primary_10_1016_j_jpdc_2015_05_008 crossref_primary_10_1016_j_nucengdes_2011_03_050 crossref_primary_10_1016_j_vlsi_2007_01_004 crossref_primary_10_1016_j_ins_2011_12_008 |
| Cites_doi | 10.1109/PROC.1966.5273 10.1145/359461.359481 10.1109/ICPP.1996.537166 10.1109/T-C.1971.223205 10.1109/ISPAN.1996.508968 10.1109/T-C.1975.224157 10.1109/TC.1983.1676201 10.1109/TC.1976.1674718 10.1109/BICTA.2008.4656716 10.1109/71.285603 10.1007/BF01840378 10.1109/TC.1979.1675216 10.1109/TC.1983.1676217 10.1109/TC.1978.1674957 10.1016/0743-7315(91)90048-E 10.1109/TC.1985.5009385 10.1109/12.16506 |
| ContentType | Journal Article |
| Copyright | Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2000 |
| Copyright_xml | – notice: Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2000 |
| DBID | RIA RIE AAYXX CITATION 7SC 7SP 8FD JQ2 L7M L~C L~D F28 FR3 |
| DOI | 10.1109/71.852399 |
| DatabaseName | IEEE All-Society Periodicals Package (ASPP) 1998–Present IEEE Electronic Library (IEL) CrossRef Computer and Information Systems Abstracts Electronics & Communications Abstracts Technology Research Database ProQuest Computer Science Collection Advanced Technologies Database with Aerospace Computer and Information Systems Abstracts Academic Computer and Information Systems Abstracts Professional ANTE: Abstracts in New Technology & Engineering Engineering Research Database |
| DatabaseTitle | CrossRef Technology Research Database Computer and Information Systems Abstracts – Academic Electronics & Communications Abstracts ProQuest Computer Science Collection Computer and Information Systems Abstracts Advanced Technologies Database with Aerospace Computer and Information Systems Abstracts Professional Engineering Research Database ANTE: Abstracts in New Technology & Engineering |
| DatabaseTitleList | Technology Research Database Computer and Information Systems Abstracts Technology Research Database Computer and Information Systems Abstracts |
| Database_xml | – sequence: 1 dbid: RIE name: IEEE Electronic Library (IEL) url: https://ieeexplore.ieee.org/ sourceTypes: Publisher |
| DeliveryMethod | fulltext_linktorsrc |
| Discipline | Engineering Computer Science |
| EISSN | 1558-2183 |
| EndPage | 474 |
| ExternalDocumentID | 2582273141 10_1109_71_852399 852399 |
| GroupedDBID | --Z -~X .DC 0R~ 29I 4.4 5GY 5VS 6IK 97E AAJGR AARMG AASAJ AAWTH ABAZT ABFSI ABQJQ ABVLG ACGFO ACIWK AENEX AETIX AGQYO AGSQL AHBIQ AI. AIBXA AKJIK AKQYR ALLEH ALMA_UNASSIGNED_HOLDINGS ASUFR ATWAV BEFXN BFFAM BGNUA BKEBE BPEOZ CS3 DU5 E.L EBS EJD HZ~ H~9 ICLAB IEDLZ IFIPE IFJZH IPLJI JAVBF LAI M43 MS~ O9- OCL P2P PQQKQ RIA RIE RNI RNS RZB TN5 TWZ UHB VH1 AAYXX CITATION 7SC 7SP 8FD JQ2 L7M L~C L~D RIG F28 FR3 |
| ID | FETCH-LOGICAL-c367t-5a73045832a2d1b14d416d9eb35dd06f023f4ca5a784f4468b01a6628bd1f5093 |
| IEDL.DBID | RIE |
| ISICitedReferencesCount | 25 |
| ISICitedReferencesURI | http://www.webofscience.com/api/gateway?GWVersion=2&SrcApp=Summon&SrcAuth=ProQuest&DestLinkType=CitingArticles&DestApp=WOS_CPL&KeyUT=000087893100003&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D |
| ISSN | 1045-9219 |
| IngestDate | Sun Sep 28 10:41:18 EDT 2025 Sun Sep 28 08:17:16 EDT 2025 Sun Sep 28 04:14:09 EDT 2025 Fri Jul 25 03:52:56 EDT 2025 Tue Nov 18 22:38:05 EST 2025 Sat Nov 29 03:35:56 EST 2025 Wed Aug 27 02:52:30 EDT 2025 |
| IsPeerReviewed | true |
| IsScholarly | true |
| Issue | 5 |
| Language | English |
| License | https://ieeexplore.ieee.org/Xplorehelp/downloads/license-information/IEEE.html |
| LinkModel | DirectLink |
| MergedId | FETCHMERGED-LOGICAL-c367t-5a73045832a2d1b14d416d9eb35dd06f023f4ca5a784f4468b01a6628bd1f5093 |
| Notes | ObjectType-Article-1 SourceType-Scholarly Journals-1 ObjectType-Feature-2 content type line 14 ObjectType-Article-2 ObjectType-Feature-1 content type line 23 |
| PQID | 920664280 |
| PQPubID | 23500 |
| PageCount | 16 |
| ParticipantIDs | proquest_miscellaneous_914631425 crossref_citationtrail_10_1109_71_852399 proquest_miscellaneous_27603366 proquest_miscellaneous_28386357 crossref_primary_10_1109_71_852399 ieee_primary_852399 proquest_journals_920664280 |
| PublicationCentury | 2000 |
| PublicationDate | 2000-05-01 |
| PublicationDateYYYYMMDD | 2000-05-01 |
| PublicationDate_xml | – month: 05 year: 2000 text: 2000-05-01 day: 01 |
| PublicationDecade | 2000 |
| PublicationPlace | New York |
| PublicationPlace_xml | – name: New York |
| PublicationTitle | IEEE transactions on parallel and distributed systems |
| PublicationTitleAbbrev | TPDS |
| PublicationYear | 2000 |
| Publisher | IEEE The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher_xml | – name: IEEE – name: The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| References | kumar (bibL045913) 1994 bibL045922 bibL045921 bibL045924 bibL045923 bibL045925 bibL045928 hwang (bibL045910) 1993 flynn (bibL04598) 1966; 54 batcher (bibL04594) 1968; 32 siegel (bibL045927) 1977 siegel (bibL045926) 1990 bibL045919 bibL045918 bibL04599 lee (bibL045916) 1995 bibL04596 bibL04595 wang (bibL045930) 1991; 3 bibL045912 bibL04597 bibL045914 knuth (bibL045911) 1973; 3 bibL045917 ajtai (bibL04591) 1983 lee (bibL045915) 1999; 26 liszka (bibL045920) 1992 akl (bibL04592) 1985 bibL045929 batcher (bibL04593) 1990 |
| References_xml | – volume: 54 start-page: 1901 year: 1966 ident: bibL04598 article-title: very high-speed computing systems publication-title: Proceedings of the IEEE doi: 10.1109/PROC.1966.5273 – start-page: 23 year: 1977 ident: bibL045927 article-title: "the universality of various types of simd machine interconnection networks publication-title: Proc Fourth Ann Symp Computer Architecture – ident: bibL045929 doi: 10.1145/359461.359481 – ident: bibL045918 doi: 10.1109/ICPP.1996.537166 – ident: bibL045928 doi: 10.1109/T-C.1971.223205 – volume: 3 year: 1973 ident: bibL045911 publication-title: The Art of Computer Programming Sorting and Searching – ident: bibL045917 doi: 10.1109/ISPAN.1996.508968 – ident: bibL045914 doi: 10.1109/T-C.1975.224157 – year: 1990 ident: bibL045926 publication-title: Interconnection Networks for Large-Scale Parallel Processing – ident: bibL04599 doi: 10.1109/TC.1983.1676201 – volume: 26 start-page: 33 year: 1999 ident: bibL045915 article-title: "design of general-purpose bitonic sorting algorithms with a fixed number of processors for shared-memory parallel computers publication-title: J KISS(A) Computer Systems and Theory – ident: bibL045923 doi: 10.1109/TC.1976.1674718 – ident: bibL045925 doi: 10.1109/BICTA.2008.4656716 – ident: bibL04596 doi: 10.1109/71.285603 – volume: 3 start-page: 58 year: 1991 ident: bibL045930 article-title: "bitonic sort with an arbitrary number of keys publication-title: Proc 1991 Int l Conf Parallel Processing – ident: bibL045924 doi: 10.1007/BF01840378 – ident: bibL045921 doi: 10.1109/TC.1979.1675216 – ident: bibL045912 doi: 10.1109/TC.1983.1676217 – ident: bibL04595 doi: 10.1109/TC.1978.1674957 – year: 1992 ident: bibL045920 article-title: "generalized bitonic and odd-even merging networks publication-title: doctoral dissertation Dept of Math and Computer Science Kent State Univ – year: 1994 ident: bibL045913 publication-title: Intro Parallel Computing Design and Analysis of Parallel Algorithms – year: 1993 ident: bibL045910 publication-title: Advanced Computer Architecture Parallelism Scalability Programmability – volume: 32 start-page: 307 year: 1968 ident: bibL04594 article-title: sorting networks and their applications publication-title: Proc Spring Joint Computer Conf AFIPS – ident: bibL04597 doi: 10.1016/0743-7315(91)90048-E – start-page: 138 year: 1995 ident: bibL045916 article-title: "simplifying multistage hardware interconnection in the bitonic sorting network publication-title: Proc Seventh IASTED/ISMM Int l Conf Parallel and Distributed Computing and Systems – year: 1990 ident: bibL04593 article-title: on bitonic sorting networks publication-title: Proc 1990 Int l conf Parallel Processing – year: 1985 ident: bibL04592 publication-title: Parallel Sorting Algorithms – ident: bibL045919 doi: 10.1109/TC.1985.5009385 – start-page: 1 year: 1983 ident: bibL04591 article-title: an $o(n \log n)$sorting network publication-title: Proc 15th Ann ACM Symp Theory of Computing – ident: bibL045922 doi: 10.1109/12.16506 |
| SSID | ssj0014504 |
| Score | 1.7345212 |
| Snippet | This paper presents bitonic sorting schemes for special-purpose parallel architectures such as sorting networks and for general-purpose parallel architectures... [...] a recirculating bitonic sorting network is presented, which is composed of one level of N/2 comparators plus an Ω-network of (log N-1) switch levels. |
| SourceID | proquest crossref ieee |
| SourceType | Aggregation Database Enrichment Source Index Database Publisher |
| StartPage | 459 |
| SubjectTerms | Communication switching Computer networks Concurrent computing Cost engineering Costs Interconnection Multiprocessor interconnection networks Networks Parallel architectures Parity Sorting Strategy Studies Switches Switching theory Time sharing computer systems Wiring |
| Title | Minimizing communication in the bitonic sort |
| URI | https://ieeexplore.ieee.org/document/852399 https://www.proquest.com/docview/920664280 https://www.proquest.com/docview/27603366 https://www.proquest.com/docview/28386357 https://www.proquest.com/docview/914631425 |
| Volume | 11 |
| WOSCitedRecordID | wos000087893100003&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D |
| hasFullText | 1 |
| inHoldings | 1 |
| isFullTextHit | |
| isPrint | |
| journalDatabaseRights | – providerCode: PRVIEE databaseName: IEEE Electronic Library (IEL) customDbUrl: eissn: 1558-2183 dateEnd: 99991231 omitProxy: false ssIdentifier: ssj0014504 issn: 1045-9219 databaseCode: RIE dateStart: 19900101 isFulltext: true titleUrlDefault: https://ieeexplore.ieee.org/ providerName: IEEE |
| link | http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV07T8MwED5BxQADhQKilIeFGBhIiePEjxEhEAuIASS2yIltKRKkqA8Gfj1nJ61A0IEtcb5I1jnnu8v5vgM4Y4XSimUmYnGiozQpTKSdKCKZoi3MEnSRnQ7NJsTDg3x5UY8tz3aohbHWhsNndugvQy7fjMqZ_1V2KTNfibkKq0LwplRrkTBIs9ApEIOLLFKohS2JEI3VpaDD5sUfpif0Uvm1AQerctv913y2YLN1HslVs9rbsGLrHnTnjRlIq6c92PjGMrgDF_dVXb1Vn3hDyu_1IKSqCfp_pECtxjEyQVd8F55vb56u76K2SUJUMi6mUaZFk_xMdGJoQVODLpZRGCNnxsTcoU12aakRJlOHsZ8sYqo5T2RhqENvge1Bpx7Vdh-IS2lsDLUIs6nRWhrBHDeUCZq4gvM-nM_ll5ctg7hvZPGah0giVrmgeSOTPpwuoO8NbcZfoJ6X6QIwHx3M1yRv9WmSK886j5FS3IeTxVNUBJ_d0LUdzSZ5InjMmJ_lUoRk0tPv9YEsQSi0G4ziNnbw59QGsN5U4vvzjofQmY5n9gjWyo9pNRkfhw_yCwP93kQ |
| linkProvider | IEEE |
| linkToHtml | http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV1LS8QwEB58gXrwsSquzyAePFhtmrZJjiIuK7qLhxW8lbRJoKBdcXc9-OudpN1FUQ_e2vQrhEknM9PJfANwynKpJEt0wMJIBXGU60BZngciRluYROgiW-WbTfB-Xzw9yYeGZ9vXwhhj_OEzc-EufS5fD4uJ-1V2KRJXiTkPi65xVlOsNUsZxInvFYjhRRJI1MOGRoiG8pLTi_rVb8bHd1P5sQV7u9JZ_9eMNmCtcR_JVb3emzBnqhasT1szkEZTW7D6hWdwC857ZVW-lB94Q4qvFSGkrAh6gCRHvcYxMkJnfBseOzeD627QtEkICpbycZAoXqc_IxVpmtNYo5OlJUbJidZhatEq27hQCBOxxehP5CFVaRqJXFOL_gLbgYVqWJldIDamodbUIMzEWimhObOppozTyOZp2oazqfyyouEQd60snjMfS4Qy4zSrZdKGkxn0tSbO-A3UcjKdAaaj-9M1yRqNGmXS8c5jrBS24Xj2FFXB5TdUZYaTURbxNGTMzfJPhGDCEfC1gfyBkGg5GMWNbO_XqR3DcnfQu8_ub_t3-7BS1-W7048HsDB-m5hDWCrex-Xo7ch_nJ-9kuGN |
| openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.atitle=Minimizing+communication+in+the+bitonic+sort&rft.jtitle=IEEE+transactions+on+parallel+and+distributed+systems&rft.au=Jae-Dong+Lee&rft.au=Batcher%2C+K.E.&rft.date=2000-05-01&rft.issn=1045-9219&rft.volume=11&rft.issue=5&rft.spage=459&rft.epage=474&rft_id=info:doi/10.1109%2F71.852399&rft.externalDBID=n%2Fa&rft.externalDocID=10_1109_71_852399 |
| thumbnail_l | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/lc.gif&issn=1045-9219&client=summon |
| thumbnail_m | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/mc.gif&issn=1045-9219&client=summon |
| thumbnail_s | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/sc.gif&issn=1045-9219&client=summon |