Hardware Implementation of a High-Accuracy and High-Throughput Rate Estimation Unit for VVC Residual Coding

In High Efficiency Video Coding standard, rate estimation based on context-based adaptive binary arithmetic coding (CABAC) typically achieves high accuracy. However, due to serial data dependencies, hardware implementation solutions suffer from lower throughput. When it comes to the latest generatio...

Full description

Saved in:

Bibliographic Details
Published in:	IEEE transactions on circuits and systems for video technology Vol. 35; no. 3; pp. 2832 - 2843
Main Authors:	Liu, Chang, Huang, Leilei, Zhang, Chenyang, Li, Wei, Hao, Zhijian, Fan, Yibo
Format:	Journal Article
Language:	English
Published:	New York IEEE 01.03.2025 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:	Accuracy Algorithms Arithmetic Arithmetic coding Binary codes CABAC Coding standards Context modeling Costs Curve fitting Encoding Estimation Hardware hardware implementation Information storage Optimization rate estimation Real time Syntactics Throughput Transforms Versatile video coding (VVC) Video compression
ISSN:	1051-8215, 1558-2205
Online Access:	Get full text
Tags:	Add Tag No Tags, Be the first to tag this record!

Abstract	In High Efficiency Video Coding standard, rate estimation based on context-based adaptive binary arithmetic coding (CABAC) typically achieves high accuracy. However, due to serial data dependencies, hardware implementation solutions suffer from lower throughput. When it comes to the latest generation video coding standard, namely Versatile Video Coding (VVC), the increased data dependency and computational complexity during the coding process pose more challenges for the hardware design of rate estimation. To solve these problems, this paper presents a hardware implementation of high-accuracy and high-throughput rate estimation unit for VVC. In terms of throughput improvement, we propose two optimization algorithms to eliminate the majority of data dependencies in coefficient coding with nearly negligible loss in Bjontegaard Delta (BD)-rate performance. To save hardware resources, we introduce a rate estimation table compression algorithm and an optimized local statistical information storage strategy. Based on these optimizations, we present a hardware implementation for the rate estimation unit and a parallel scheme for the rate-distortion optimization process. The proposed algorithm shows an increase of 0.29% in the BD-rate compared to the VVC test model 19.2. Synthesis results show that the proposed design supports real-time coding of <inline-formula> <tex-math notation="LaTeX">7680\times 4320 </tex-math></inline-formula>@30fps at 500MHz operating frequency. These results indicate that our proposed design performs well in terms of BD-rate performance and throughput. To the best of our knowledge, this is the first hardware implementation of rate estimation for VVC.
AbstractList	In High Efficiency Video Coding standard, rate estimation based on context-based adaptive binary arithmetic coding (CABAC) typically achieves high accuracy. However, due to serial data dependencies, hardware implementation solutions suffer from lower throughput. When it comes to the latest generation video coding standard, namely Versatile Video Coding (VVC), the increased data dependency and computational complexity during the coding process pose more challenges for the hardware design of rate estimation. To solve these problems, this paper presents a hardware implementation of high-accuracy and high-throughput rate estimation unit for VVC. In terms of throughput improvement, we propose two optimization algorithms to eliminate the majority of data dependencies in coefficient coding with nearly negligible loss in Bjontegaard Delta (BD)-rate performance. To save hardware resources, we introduce a rate estimation table compression algorithm and an optimized local statistical information storage strategy. Based on these optimizations, we present a hardware implementation for the rate estimation unit and a parallel scheme for the rate-distortion optimization process. The proposed algorithm shows an increase of 0.29% in the BD-rate compared to the VVC test model 19.2. Synthesis results show that the proposed design supports real-time coding of <inline-formula> <tex-math notation="LaTeX">7680\times 4320 </tex-math></inline-formula>@30fps at 500MHz operating frequency. These results indicate that our proposed design performs well in terms of BD-rate performance and throughput. To the best of our knowledge, this is the first hardware implementation of rate estimation for VVC. In High Efficiency Video Coding standard, rate estimation based on context-based adaptive binary arithmetic coding (CABAC) typically achieves high accuracy. However, due to serial data dependencies, hardware implementation solutions suffer from lower throughput. When it comes to the latest generation video coding standard, namely Versatile Video Coding (VVC), the increased data dependency and computational complexity during the coding process pose more challenges for the hardware design of rate estimation. To solve these problems, this paper presents a hardware implementation of high-accuracy and high-throughput rate estimation unit for VVC. In terms of throughput improvement, we propose two optimization algorithms to eliminate the majority of data dependencies in coefficient coding with nearly negligible loss in Bjontegaard Delta (BD)-rate performance. To save hardware resources, we introduce a rate estimation table compression algorithm and an optimized local statistical information storage strategy. Based on these optimizations, we present a hardware implementation for the rate estimation unit and a parallel scheme for the rate-distortion optimization process. The proposed algorithm shows an increase of 0.29% in the BD-rate compared to the VVC test model 19.2. Synthesis results show that the proposed design supports real-time coding of [Formula Omitted]@30fps at 500MHz operating frequency. These results indicate that our proposed design performs well in terms of BD-rate performance and throughput. To the best of our knowledge, this is the first hardware implementation of rate estimation for VVC.
Author	Zhang, Chenyang Li, Wei Huang, Leilei Hao, Zhijian Fan, Yibo Liu, Chang
Author_xml	– sequence: 1 givenname: Chang orcidid: 0000-0002-1897-8862 surname: Liu fullname: Liu, Chang organization: State Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, China – sequence: 2 givenname: Leilei orcidid: 0000-0002-8900-4109 surname: Huang fullname: Huang, Leilei email: llhuang@cee.ecnu.edu.cn organization: Institute of Microelectronic Circuits and Systems, East China Normal University, Shanghai, China – sequence: 3 givenname: Chenyang surname: Zhang fullname: Zhang, Chenyang organization: State Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, China – sequence: 4 givenname: Wei orcidid: 0000-0002-6861-7117 surname: Li fullname: Li, Wei organization: State Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, China – sequence: 5 givenname: Zhijian orcidid: 0000-0002-7892-5973 surname: Hao fullname: Hao, Zhijian organization: State Key Discipline Laboratory of Wide Band-Gap Semiconductor Technology, School of Microelectronics, Xidian University, Xi'an, China – sequence: 6 givenname: Yibo orcidid: 0000-0003-2523-8261 surname: Fan fullname: Fan, Yibo email: fanyibo@fudan.edu.cn organization: State Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, China
BookMark	eNp9kUFLwzAUx4NMcE6_gHgIeO5M0qbJjqNMNxgIs9s1pGm6ZXbNTFNk397M7iAevLw8wv-Xx_vlFgwa22gAHjAaY4wmz3n2vsnHBJFkHCecEZJcgSGmlEeEIDoIPaI44gTTG3DbtnuEcMITNgQfc-nKL-k0XByOtT7oxktvbANtBSWcm-0umirVOalOUDZlf5PvnO22u2Pn4Up6DWetN4ceWzfGw8o6uNlkcKVbU3ayhpktTbO9A9eVrFt9fzlHYP0yy7N5tHx7XWTTZaTiNPURxhPNizSUlDBUlCVRFS51FVMiqUoV4yGnU8xVggguOCkShiqZlBRrqeIqHoGn_t2js5-dbr3Y2841YaSIMQt6JhSxkOJ9Sjnbtk5XQpl-d--kqQVG4qxW_KgVZ7Xiojag5A96dEGAO_0PPfaQ0Vr_AljMwl_E3-9fh6E
CODEN	ITCTEM
CitedBy_id	crossref_primary_10_1007_s11554_025_01733_8 crossref_primary_10_1007_s11227_025_07736_3
Cites_doi	10.1109/CCNC.2013.6488534 10.1109/TCSVT.2019.2934752 10.1109/TCSVT.2021.3093579 10.1109/TCSVT.2021.3101953 10.1109/TCSVT.2021.3072202 10.1109/TBC.2021.3077771 10.1109/ICASSP43922.2022.9747694 10.1109/ICDSP.2015.7251917 10.1109/ISCAS48785.2022.9937635 10.1109/LASCAS60203.2024.10506158 10.1109/ISCAS46773.2023.10182170 10.1109/PACRIM.2017.8121907 10.1007/s11554-015-0549-8 10.1109/TIP.2021.3083447 10.1109/TCSVT.2021.3088134 10.1109/TCSVT.2010.2045803 10.1109/TCSVT.2019.2904198 10.1109/ACCESS.2020.3000565 10.1109/TCSVT.2018.2830126 10.1109/VCIP56404.2022.10008905 10.1109/TVLSI.2023.3245291 10.1109/TCSVT.2012.2221191 10.1109/LASCAS56464.2023.10108393 10.1109/TCSVT.2015.2428571 10.1109/ISCAS.2017.8050459
ContentType	Journal Article
Copyright	Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2025
Copyright_xml	– notice: Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2025
DBID	97E RIA RIE AAYXX CITATION 7SC 7SP 8FD JQ2 L7M L~C L~D
DOI	10.1109/TCSVT.2024.3487224
DatabaseName	IEEE Xplore (IEEE) IEEE All-Society Periodicals Package (ASPP) 1998–Present IEEE Electronic Library (IEL) CrossRef Computer and Information Systems Abstracts Electronics & Communications Abstracts Technology Research Database ProQuest Computer Science Collection Advanced Technologies Database with Aerospace Computer and Information Systems Abstracts Academic Computer and Information Systems Abstracts Professional
DatabaseTitle	CrossRef Technology Research Database Computer and Information Systems Abstracts – Academic Electronics & Communications Abstracts ProQuest Computer Science Collection Computer and Information Systems Abstracts Advanced Technologies Database with Aerospace Computer and Information Systems Abstracts Professional
DatabaseTitleList	Technology Research Database
Database_xml	– sequence: 1 dbid: RIE name: IEEE Electronic Library (IEL) url: https://ieeexplore.ieee.org/ sourceTypes: Publisher
DeliveryMethod	fulltext_linktorsrc
Discipline	Engineering
EISSN	1558-2205
EndPage	2843
ExternalDocumentID	10_1109_TCSVT_2024_3487224 10737148
Genre	orig-research
GrantInformation_xml	– fundername: Fudan-Zhongxing Telecom Equipment Joint Laboratory – fundername: National Natural Science Foundation of China grantid: 62031009 funderid: 10.13039/501100001809 – fundername: Alibaba Innovative Research Program – fundername: Alibaba Research Fellow Program grantid: 62031009 funderid: 10.13039/501100001809 – fundername: National Key Research and Development Program of China grantid: 2023YFB4502802
GroupedDBID	-~X 0R~ 29I 4.4 5GY 5VS 6IK 97E AAJGR AARMG AASAJ AAWTH ABAZT ABQJQ ABVLG ACGFO ACGFS ACIWK AENEX AETIX AGQYO AGSQL AHBIQ AI. AIBXA AKJIK AKQYR ALLEH ALMA_UNASSIGNED_HOLDINGS ASUFR ATWAV BEFXN BFFAM BGNUA BKEBE BPEOZ CS3 DU5 EBS EJD HZ~ H~9 ICLAB IFIPE IFJZH IPLJI JAVBF LAI M43 O9- OCL P2P RIA RIE RNS RXW TAE TN5 VH1 AAYXX CITATION 7SC 7SP 8FD JQ2 L7M L~C L~D
ID	FETCH-LOGICAL-c366t-119e8b69e86270bdd2cf1def352a5c6c78c36e618c4021b82b470fa4d51eac3f3
IEDL.DBID	RIE
ISICitedReferencesCount	1
ISICitedReferencesURI	http://www.webofscience.com/api/gateway?GWVersion=2&SrcApp=Summon&SrcAuth=ProQuest&DestLinkType=CitingArticles&DestApp=WOS_CPL&KeyUT=001439628600012&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D
ISSN	1051-8215
IngestDate	Tue Jul 22 18:41:14 EDT 2025 Tue Nov 18 21:55:22 EST 2025 Sat Nov 29 08:14:47 EST 2025 Wed Aug 27 01:48:43 EDT 2025
IsPeerReviewed	true
IsScholarly	true
Issue	3
Language	English
License	https://ieeexplore.ieee.org/Xplorehelp/downloads/license-information/IEEE.html https://doi.org/10.15223/policy-029 https://doi.org/10.15223/policy-037
LinkModel	DirectLink
MergedId	FETCHMERGED-LOGICAL-c366t-119e8b69e86270bdd2cf1def352a5c6c78c36e618c4021b82b470fa4d51eac3f3
Notes	ObjectType-Article-1 SourceType-Scholarly Journals-1 ObjectType-Feature-2 content type line 14
ORCID	0000-0002-8900-4109 0000-0002-6861-7117 0000-0002-1897-8862 0000-0003-2523-8261 0000-0002-7892-5973
PQID	3174879507
PQPubID	85433
PageCount	12
ParticipantIDs	ieee_primary_10737148 proquest_journals_3174879507 crossref_citationtrail_10_1109_TCSVT_2024_3487224 crossref_primary_10_1109_TCSVT_2024_3487224
PublicationCentury	2000
PublicationDate	2025-03-01
PublicationDateYYYYMMDD	2025-03-01
PublicationDate_xml	– month: 03 year: 2025 text: 2025-03-01 day: 01
PublicationDecade	2020
PublicationPlace	New York
PublicationPlace_xml	– name: New York
PublicationTitle	IEEE transactions on circuits and systems for video technology
PublicationTitleAbbrev	TCSVT
PublicationYear	2025
Publisher	IEEE The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher_xml	– name: IEEE – name: The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
References	ref13 ref12 ref15 ref14 ref11 ref10 ref2 ref1 ref17 ref16 ref18 Tsai (ref20) Bossen (ref30) 2019 Bjøntegaard (ref26) 2001 ref24 ref23 ref25 Chuang (ref28) 2018 ref22 ref21 ref27 ref29 ref8 ref7 ref9 ref4 ref3 Bossen (ref19) 2011 ref6 ref5
References_xml	– ident: ref12 doi: 10.1109/CCNC.2013.6488534 – ident: ref8 doi: 10.1109/TCSVT.2019.2934752 – ident: ref23 doi: 10.1109/TCSVT.2021.3093579 – ident: ref1 doi: 10.1109/TCSVT.2021.3101953 – volume-title: CE1: Table-Based Bit Estimation for CABAC year: 2011 ident: ref19 – ident: ref24 doi: 10.1109/TCSVT.2021.3072202 – ident: ref15 doi: 10.1109/TBC.2021.3077771 – ident: ref16 doi: 10.1109/ICASSP43922.2022.9747694 – ident: ref13 doi: 10.1109/ICDSP.2015.7251917 – ident: ref6 doi: 10.1109/ISCAS48785.2022.9937635 – ident: ref25 doi: 10.1109/LASCAS60203.2024.10506158 – ident: ref10 doi: 10.1109/ISCAS46773.2023.10182170 – ident: ref14 doi: 10.1109/PACRIM.2017.8121907 – ident: ref21 doi: 10.1007/s11554-015-0549-8 – volume-title: Calculation of Average PSNR Differences Between RD Curves year: 2001 ident: ref26 – ident: ref5 doi: 10.1109/TIP.2021.3083447 – ident: ref27 doi: 10.1109/TCSVT.2021.3088134 – ident: ref11 doi: 10.1109/TCSVT.2010.2045803 – ident: ref3 doi: 10.1109/TCSVT.2019.2904198 – ident: ref4 doi: 10.1109/ACCESS.2020.3000565 – ident: ref22 doi: 10.1109/TCSVT.2018.2830126 – volume-title: CE7-related: Constraints on Context-Coded Bins for Coefficient Coding year: 2018 ident: ref28 – volume-title: JVET Common Test Conditions and Software Reference Configurations for SDR Video year: 2019 ident: ref30 – ident: ref29 doi: 10.1109/VCIP56404.2022.10008905 – start-page: C188 volume-title: Proc. Symp. VLSI Circuits ident: ref20 article-title: A 1062 Mpixels/s 8192×4320p high efficiency video coding (H.265) encoder chip – ident: ref9 doi: 10.1109/TVLSI.2023.3245291 – ident: ref2 doi: 10.1109/TCSVT.2012.2221191 – ident: ref7 doi: 10.1109/LASCAS56464.2023.10108393 – ident: ref17 doi: 10.1109/TCSVT.2015.2428571 – ident: ref18 doi: 10.1109/ISCAS.2017.8050459
SSID	ssj0014847
Score	2.4684935
Snippet	In High Efficiency Video Coding standard, rate estimation based on context-based adaptive binary arithmetic coding (CABAC) typically achieves high accuracy....
SourceID	proquest crossref ieee
SourceType	Aggregation Database Enrichment Source Index Database Publisher
StartPage	2832
SubjectTerms	Accuracy Algorithms Arithmetic Arithmetic coding Binary codes CABAC Coding standards Context modeling Costs Curve fitting Encoding Estimation Hardware hardware implementation Information storage Optimization rate estimation Real time Syntactics Throughput Transforms Versatile video coding (VVC) Video compression
Title	Hardware Implementation of a High-Accuracy and High-Throughput Rate Estimation Unit for VVC Residual Coding
URI	https://ieeexplore.ieee.org/document/10737148 https://www.proquest.com/docview/3174879507
Volume	35
WOSCitedRecordID	wos001439628600012&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D
hasFullText	1
inHoldings	1
isFullTextHit
isPrint
journalDatabaseRights	– providerCode: PRVIEE databaseName: IEEE Electronic Library (IEL) customDbUrl: eissn: 1558-2205 dateEnd: 99991231 omitProxy: false ssIdentifier: ssj0014847 issn: 1051-8215 databaseCode: RIE dateStart: 19910101 isFulltext: true titleUrlDefault: https://ieeexplore.ieee.org/ providerName: IEEE
link	http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV1dS8MwFA1u-KAPfk6cTsmDb9LZjyxJH8eY-CBD5hx7K2lyC6K2Yx-K_96btBsTUfCllJBA6Wlyz21yziXkiqW-SWVozQdBegwpv6egI7xUd4yvJAjfOMv8ezEYyMkkfqjE6k4LAwDu8Bm07a3byzeFXtpfZTjDhTWYkzVSE4KXYq31lgGTrpoY8oXAkxjIVgoZP74Z9R7HI8wFQ9aOkKCHIfsWhVxZlR9rsQswt_v_fLQDslcxSdotoT8kW5Afkd0Nf8Fj8mL35T_UDKgzAX6rdEY5LTKqqD3i4XW1Xs6U_qQqN2XLqKzcM10u6BCJKO3jIlDqG6klqBRZLh2Pe3QIcyfkor3Cxr8Gebrtj3p3XlVdwdMR5wsvCGKQKccLD4WfGhPqLDCQISNTHc21kNgPeCA1ppgB4pky4WeKmU6Ai3WURSeknhc5nBIaYqYLVuOqkJ5pSFWkZCywhWNyB4w3SbB624murMdtBYzXxKUgfpw4hBKLUFIh1CTX6zHT0njjz94Ni8lGzxKOJmmtUE2qyTlPkDIxW2PdF2e_DDsnO6Gt8-vOmrVIfTFbwgXZ1u-L5_ns0n13X2YZ1Hc
linkProvider	IEEE
linkToHtml	http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV1Na9wwEB3atND0kLbJhm6bNjr0FpzIsmzJx2VJSOlmKamz5GZkaQwhrTfsR0P-fUeyd0kICfRijJDA-FmaN5beG4BvsuKu0sKbD6KOJFH-yGCqosqmjhuNirtgmT9S47G-vMx_dmL1oIVBxHD4DA_9bdjLd1O79L_KaIYrbzCnX8KrVErBW7nWetNA6lBPjBhDHGkKZSuNDM-PiuGvSUHZoJCHCVF0IeSDOBQKqzxajUOIOXn3nw_3HrY6LskGLfgf4AU22_D2nsPgDlz7nflbM0MWbID_dEqjhk1rZpg_5BENrF3OjL1jpnFtS9HW7rlZLtg5UVF2TMtAq3BknqIy4rlsMhmyc5wHKRcbTn0E7MHFyXExPI26-gqRTbJsEcVxjrrK6JIJxSvnhK1jhzVxMpPazCpN_TCLtaUkMyZEK6l4baRLY1qukzrZhY1m2uBHYIJyXfQqV0MEzWJlEqNzRS0ZpXcosz7Eq7dd2s583NfA-F2GJITnZUCo9AiVHUJ9OFiPuWmtN57t3fOY3OvZwtGHvRWqZTc95yWRJumrrHP16Ylh-_DmtDgblaPv4x-fYVP4qr_h5NkebCxmS_wCr-3fxdV89jV8g_8AnHrXvg
openUrl	ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.atitle=Hardware+Implementation+of+a+High-Accuracy+and+High-Throughput+Rate+Estimation+Unit+for+VVC+Residual+Coding&rft.jtitle=IEEE+transactions+on+circuits+and+systems+for+video+technology&rft.au=Liu%2C+Chang&rft.au=Huang%2C+Leilei&rft.au=Zhang%2C+Chenyang&rft.au=Li%2C+Wei&rft.date=2025-03-01&rft.pub=The+Institute+of+Electrical+and+Electronics+Engineers%2C+Inc.+%28IEEE%29&rft.issn=1051-8215&rft.eissn=1558-2205&rft.volume=35&rft.issue=3&rft.spage=2832&rft_id=info:doi/10.1109%2FTCSVT.2024.3487224&rft.externalDBID=NO_FULL_TEXT
thumbnail_l	http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/lc.gif&issn=1051-8215&client=summon
thumbnail_m	http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/mc.gif&issn=1051-8215&client=summon
thumbnail_s	http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/sc.gif&issn=1051-8215&client=summon