Fine grain pipeline architecture for high performance phase-based optical flow computation

Accurate motion analysis of real life sequences is a very active research field due to its multiple potential applications. Currently, new technologies offer us very fast and accurate sensors that provide a huge quantity of data per second. Processing these data streams is very expensive (in terms o...

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Vydáno v:Journal of systems architecture Ročník 56; číslo 11; s. 577 - 587
Hlavní autoři: Tomasi, M., Barranco, F., Vanegas, M., Díaz, J., Ros, E.
Médium: Journal Article
Jazyk:angličtina
Vydáno: Amsterdam Elsevier B.V 01.11.2010
Elsevier Sequoia S.A
Témata:
Algorithms
Architecture
Computation
Computer architecture
Devices
Embedded and real-time systems
FPGA
Frames
Hardware
High performance computing
Illumination
Optical flow
Parallel processing
Studies
Systems design
FPGA
Optical flow
Embedded and real-time systems
ISSN:1383-7621, 1873-6165
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Shrnutí:Accurate motion analysis of real life sequences is a very active research field due to its multiple potential applications. Currently, new technologies offer us very fast and accurate sensors that provide a huge quantity of data per second. Processing these data streams is very expensive (in terms of computing power) for general purpose processors and therefore, is beyond processing capabilities of most current embedded devices. In this work, we present a specific hardware architecture that implements a robust optical flow algorithm able to process input video sequences at a high frame rate and high resolution, up to 160 fps for VGA images. We describe a superpipelined datapath of more than 85 stages (some of them configured with superscalar units able to process several data in parallel). Therefore, we have designed an intensive parallel processing engine. System speed (frames per second) produces fine optical flow estimations (by constraining the actual motion ranges between consecutive frames) and the phase-based method confers the system robustness to image noise or illumination changes. In this work, we analyze the architecture of different frame rates and input image noise levels. We compare the results with other approaches in the state of the art and validate our implementation using several hardware platforms.
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ISSN:1383-7621
1873-6165
DOI:10.1016/j.sysarc.2010.07.012