An Iterative Algorithm for Hardware-Software Partitioning, Hardware Design Space Exploration and Scheduling
The paper proposes a novel heuristic technique for integrated hardware-software partitioning, hardware design space exploration and scheduling. The technique maps an application specified as a task graph on a heterogeneous architecture with an objective to minimize the latency of the task graph subj...
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| Published in: | Design automation for embedded systems Vol. 5; no. 3-4; pp. 281 - 293 |
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| Main Authors: | , |
| Format: | Journal Article |
| Language: | English |
| Published: |
01.08.2000
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| ISSN: | 0929-5585, 1572-8080 |
| Online Access: | Get full text |
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| Abstract | The paper proposes a novel heuristic technique for integrated hardware-software partitioning, hardware design space exploration and scheduling. The technique maps an application specified as a task graph on a heterogeneous architecture with an objective to minimize the latency of the task graph subject to the area constraint on the hardware coprocessor. The technique uses an iterative approach where the partitioner decides the processor mapping and HW design points of some tasks. The scheduler then simultaneously decides the processor mapping, HW design point and schedule time of the remaining tasks. There exists a tight coupling between the two design stages allowing them to produce superior quality designs in fewer iterations. The technique accounts for the time overheads due to inter-processor/intra-processor communication and shared memory access conflicts. It can therefore be used for both communication intensive and computation intensive applications. The technique also considers dynamic reconfiguration capability of the hardware coprocessor. The technique performs tradeoff analysis and maps hardware tasks to mutually exclusive temporal segments if this results in lower latency. The effectiveness of the technique is demonstrated by a case study of the JPEG image compression algorithm, comparison with an optimal ILP based approach and experimentation with synthetic graphs. |
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| AbstractList | The paper proposes a novel heuristic technique for integrated hardware-software partitioning, hardware design space exploration and scheduling. The technique maps an application specified as a task graph on a heterogeneous architecture with an objective to minimize the latency of the task graph subject to the area constraint on the hardware coprocessor. The technique uses an iterative approach where the partitioner decides the processor mapping and HW design points of some tasks. The scheduler then simultaneously decides the processor mapping, HW design point and schedule time of the remaining tasks. There exists a tight coupling between the two design stages allowing them to produce superior quality designs in fewer iterations. The technique accounts for the time overheads due to inter-processor/intra-processor communication and shared memory access conflicts. It can therefore be used for both communication intensive and computation intensive applications. The technique also considers dynamic reconfiguration capability of the hardware coprocessor. The technique performs tradeoff analysis and maps hardware tasks to mutually exclusive temporal segments if this results in lower latency. The effectiveness of the technique is demonstrated by a case study of the JPEG image compression algorithm, comparison with an optimal ILP based approach and experimentation with synthetic graphs. |
| Author | Vemuri, Ranga Chatha, Karam S. |
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| CitedBy_id | crossref_primary_10_1155_2008_259686 crossref_primary_10_1016_j_vlsi_2009_06_002 crossref_primary_10_1016_j_sysarc_2007_09_001 crossref_primary_10_4018_jertcs_2012010101 crossref_primary_10_1109_TVLSI_2006_886411 crossref_primary_10_1007_s10766_013_0283_4 crossref_primary_10_1023_A_1016567828852 crossref_primary_10_1504_IJCAT_2009_028042 |
| Cites_doi | 10.1023/A:1008872518365 10.1145/307418.307460 10.1007/3-540-60294-1_134 10.1109/54.245964 10.1109/92.748204 10.1145/309847.310010 10.1109/43.728914 10.1109/54.232470 10.1109/71.503776 |
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| EndPage | 293 |
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| References | R. Gupta (262658_CR6) 1993; 10 Y. Kwok (262658_CR9) 1996; 7 262658_CR1 262658_CR2 262658_CR7 262658_CR8 262658_CR3 262658_CR4 262658_CR5 262658_CR11 A. Kalavade (262658_CR10) 1997; 2 262658_CR13 262658_CR12 262658_CR15 262658_CR14 |
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