Implementation of a Reduced Decoding Algorithm Complexity for Quasi-Cyclic Split-Row Threshold Low-Density Parity-Check Decoders

We propose two decoding algorithms for quasi-cyclic LDPC codes (QC-LDPC) and implement the more efficient one in this paper. These algorithms depend on the split row for the layered decoding method applied to the Min-Sum (MS) algorithm. We designate the first algorithm “Split-Row Layered Min-Sum” (S...

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Bibliographic Details
Published in:Information (Basel) Vol. 15; no. 11; p. 684
Main Authors: Mejmaa, Bilal, Aqil, Chakir, Akharraz, Ismail, Ahaitouf, Abdelaziz
Format: Journal Article
Language:English
Published: Basel MDPI AG 01.11.2024
Subjects:
Algorithms
Co-design
Codes
Complexity
Decoders
Decoding
Error correcting codes
FPGA implementation
layered decoding
LDPC codes
Low density parity check codes
min-sum
Parity
Satellite communications
Specific gravity
split row
New York
United States
ISSN:2078-2489, 2078-2489
Online Access:Get full text
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Summary:We propose two decoding algorithms for quasi-cyclic LDPC codes (QC-LDPC) and implement the more efficient one in this paper. These algorithms depend on the split row for the layered decoding method applied to the Min-Sum (MS) algorithm. We designate the first algorithm “Split-Row Layered Min-Sum” (SRLMS), and the second algorithm “Split-Row Threshold Layered Min-Sum” (SRTLMS). A threshold message passes from one partition to another in SRTLMS, minimizing the gap from the MS and achieving a binary error rate of 3 × 10−5 with Imax = 4 as the maximum number of iterations, resulting in a decrease of 0.25 dB. The simulation’s findings indicate that the SRTLMS is the most efficient variant decoding algorithm for LDPC codes, thanks to its compromise between performance and complexity. This paper presents the two invented algorithms and a comprehensive study of the co-design and implementation of the SRTLMS algorithm. We executed the implementation on a Xilinx Kintex-7 XC7K160 FPGA, achieving a maximum operating frequency of 101 MHz and a throughput of 606 Mbps.
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ISSN:2078-2489
2078-2489
DOI:10.3390/info15110684