PRECISION: A Reconfigurable SIMD/MIMD Coprocessor for Computer Vision Systems-on-Chip

Computer vision applications have a large disparity in operations, data representation and memory access patterns from the early vision stages to the final classification and recognition stages. A hardware system for computer vision has to provide high flexibility without compromising performance, e...

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Vydáno v:IEEE transactions on computers Ročník 65; číslo 8; s. 2548 - 2561
Hlavní autoři: Nieto, Alejandro, Vilarino, David L., Brea, Victor M.
Médium: Journal Article
Jazyk:angličtina
Vydáno: New York IEEE 01.08.2016
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Témata:
Architecture (computers)
Arrays
Classification
Computer vision
Coprocessors
embedded computer vision
Flexibility
FPGA
Hardware
Parallel processing
parallel processors
Program processors
Reconfigurable hardware
Registers
Tasks
Vision
ISSN:0018-9340, 1557-9956
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Shrnutí:Computer vision applications have a large disparity in operations, data representation and memory access patterns from the early vision stages to the final classification and recognition stages. A hardware system for computer vision has to provide high flexibility without compromising performance, exploiting massively spatial-parallel operations but also keeping a high throughput on data-dependent and complex program flows. Furthermore, the architecture must be modular, scalable and easy to adapt to the needs of different applications. Keeping this in mind, a hybrid SIMD/MIMD architecture for embedded computer vision is proposed. It consists of a coprocessor designed to provide fast and flexible computation of demanding image processing tasks of vision applications. A 32-bit 128-unit device was prototyped on a Virtex-6 FPGA which delivers a peak performance of 19.6 GOP/s and 7.2 W of power dissipation.
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ISSN:0018-9340
1557-9956
DOI:10.1109/TC.2015.2493527