Correct program parallelisations

A commonly used approach to develop deterministic parallel programs is to augment a sequential program with compiler directives that indicate which program blocks may potentially be executed in parallel. This paper develops a verification technique to reason about such compiler directives, in partic...

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Vydané v:	International journal on software tools for technology transfer Ročník 23; číslo 5; s. 741 - 763
Hlavní autori:	Blom, S., Darabi, S., Huisman, M., Safari, M.
Médium:	Journal Article
Jazyk:	English
Vydavateľské údaje:	Berlin/Heidelberg Springer Berlin Heidelberg 01.10.2021 Springer Nature B.V
Predmet:	Compilers Composition Computer Science Parallel programming Programming languages Representations Semantics Software Software Engineering Software Engineering/Programming and Operating Systems Syntax Theory of Computation Verification Software verification Parallelisation Deterministic parallel programming
ISSN:	1433-2779, 1433-2787
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Abstract	A commonly used approach to develop deterministic parallel programs is to augment a sequential program with compiler directives that indicate which program blocks may potentially be executed in parallel. This paper develops a verification technique to reason about such compiler directives, in particular to show that they do not change the behaviour of the program. Moreover, the verification technique is tool-supported and can be combined with proving functional correctness of the program. To develop our verification technique, we propose a simple intermediate representation (syntax and semantics) that captures the main forms of deterministic parallel programs. This language distinguishes three kinds of basic blocks: parallel, vectorised and sequential blocks, which can be composed using three different composition operators: sequential, parallel and fusion composition. We show how a widely used subset of OpenMP can be encoded into this intermediate representation. Our verification technique builds on the notion of iteration contract to specify the behaviour of basic blocks; we show that if iteration contracts are manually specified for single blocks, then that is sufficient to automatically reason about data race freedom of the composed program. Moreover, we also show that it is sufficient to establish functional correctness on a linearised version of the original program to conclude functional correctness of the parallel program. Finally, we exemplify our approach on an example OpenMP program, and we discuss how tool support is provided.
AbstractList	A commonly used approach to develop deterministic parallel programs is to augment a sequential program with compiler directives that indicate which program blocks may potentially be executed in parallel. This paper develops a verification technique to reason about such compiler directives, in particular to show that they do not change the behaviour of the program. Moreover, the verification technique is tool-supported and can be combined with proving functional correctness of the program. To develop our verification technique, we propose a simple intermediate representation (syntax and semantics) that captures the main forms of deterministic parallel programs. This language distinguishes three kinds of basic blocks: parallel, vectorised and sequential blocks, which can be composed using three different composition operators: sequential, parallel and fusion composition. We show how a widely used subset of OpenMP can be encoded into this intermediate representation. Our verification technique builds on the notion of iteration contract to specify the behaviour of basic blocks; we show that if iteration contracts are manually specified for single blocks, then that is sufficient to automatically reason about data race freedom of the composed program. Moreover, we also show that it is sufficient to establish functional correctness on a linearised version of the original program to conclude functional correctness of the parallel program. Finally, we exemplify our approach on an example OpenMP program, and we discuss how tool support is provided.
Author	Blom, S. Huisman, M. Safari, M. Darabi, S.
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Cites_doi	10.2168/LMCS-11(1:2)2015 10.1145/2491522.2491525 10.1145/1925844.1926416 10.1145/2517327.2442529 10.1016/j.jpdc.2004.11.010 10.1145/2818638 10.1007/978-3-642-19718-5_23 10.1007/978-3-319-11454-5_7 10.1145/1345206.1345234 10.1007/978-3-662-46675-9_14 10.1109/IISWC.2009.5306797 10.1007/978-3-030-34968-4_5 10.1007/3-540-44898-5_4 10.1007/978-3-662-49122-5_2 10.1007/978-3-642-38856-9_16 10.1007/978-3-319-57288-8_17 10.1007/978-3-540-89330-1_13 10.1145/2160910.2160911 10.1145/2103621.2103694 10.1145/1047659.1040327
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References	Bubel, R., Hähnle, R., Heydari Tabar, A.: A program logic for dependence analysis. In: Ahrendt, W., Tapia Tarifa, S.L. (eds.) Integrated Formal Methods. Springer International Publishing, Cham, pp. 83–100 (2019) Salamanca, J., Mattos, L., Araujo, G.: Loop-carried dependence verification in OpenMP. In: International Workshop on OpenMP 2014, pp. 87–102 (2014) Hurlin, C.: Specification and Verification of Multithreaded Object-Oriented Programs with Separation Logic. PhD thesis, Université Nice Sophia Antipolis (2009) Viper project website. http://www.pm.inf.ethz.ch/research/viper von Praun, C., Bordawekar, R., Cascaval, C.: Modeling optimistic concurrency using quantitative dependence analysis. In: Proceedings of the 13th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, pp. 185–196 (2008) Amighi, A., Haack, C., Huisman, M., Hurlin, C.: Permission-based separation logic for multithreaded Java programs. LMCS 11(1), (2015) Barthe, G., Crespo, J.M., Gulwani, S., Kunz, C., Marron, M.: From relational verification to SIMD loop synthesis. In: PPoPP, pp. 123–134 (2013) Haack, C., Huisman, M., Hurlin, C.: Reasoning about Java’s reentrant locks. In: Ramalingam, G., (ed.) Programming Languages and Systems, 6th Asian Symposium, APLAS 2008, Bangalore, India, December 9–11, 2008. Proceedings, Volume 5356 of LNCS. Springer, pp. 171–187 (2008) Raychev, V., Vechev, M., Yahav, E.: Automatic synthesis of deterministic concurrency. In: Static Analysis—20th International Symposium, SAS 2013, Seattle, WA, USA, June 20–22, 2013. Proceedings. Springer, pp. 283–303 (2013) SmansJJacobsBPiessensFImplicit dynamic framesACM Trans. Program. Lang. Syst.20123412:12:5810.1145/2160910.2160911 Dodds, M., Jagannathan, S., Parkinson, M.J.: Modular reasoning for deterministic parallelism. In ACM SIGPLAN Notices, pp. 259–270 (2011) Botincan, M., Dodds, M., Jagannathan, S.: Resource-sensitive synchronization inference by abduction. In: Field, J., Hicks, M. (eds.) Principles of Programming Languages (POPL 2012), pp. 309–322 (2012) Che, S., Boyer, M., Meng, J., Tarjan, D., Sheaffer, J.W., Lee, S.-H., Skadron, K.: Rodinia: A benchmark suite for heterogeneous computing. In Workload Characterization. IISWC 2009, pp. 44–54 (2009) Parkinson, M., Summers, A.: The relationship between separation logic and implicit dynamic frames. In Barthe, G. (ed.) Programming Languages and Systems—20th European Symposium on Programming, ESOP 2011, Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2011, Saarbrücken, Germany, March 26–April 3, 2011. Proceedings, volume 6602 of LNCS. Springer, pp. 439–458 (2011) Aviram, A., Ford, B.: Deterministic OpenMP for Race-free Parallelism. In HotPar’11 (2011) Boyland, J.: Checking interference with fractional permissions. In: SAS, Volume 2694 of LNCS. Springer, pp. 55–72 (2003) Müller, P., Schwerhoff, M., Summers, A.: Viper—a verification infrastructure for permission-based reasoning. In VMCAI (2016) BergerMJAftosmisMJMarshallDDMurmanSMPerformance of a new CFD flow solver using a hybrid programming paradigmJ. Parallel Distrib. Comput.200565441442310.1016/j.jpdc.2004.11.010 Leavens, G., Poll, E., Clifton, C., Cheon, Y., Ruby, C., Cok, D.R., Müller, P., Kiniry, J., Chalin, P.: JML Reference Manual (2007). Dept. of Computer Science, Iowa State University. http://www.jmlspecs.org Blom, S., Darabi, S., Huisman, M.: Verification of loop parallelisations. In: Egyed, A., Schaefer, I. (eds.) FASE, Volume 9033 of LNCS. Springer, pp. 202–217 (2015) Darabi, S., Blom, S., Huisman, M.: A verification technique for deterministic parallel programs. In: Barrett, C., Davies, M., Kahsai, T. (eds.) NASA Formal Methods (NFM), Volume 10227 of LNCS, pp. 247–264 (2017) LLNL OpenMP Benchmarks. Last accessed 28 Nov 2016. https://asc.llnl.gov/CORAL-benchmarks DoddsMJagannathanSParkinsonMJSvendsenKBirkedalLVerifying custom synchronization constructs using higher-order separation logicACM Trans. Program. Lang. Syst.20163824:14:7210.1145/2818638 Jin, H.-Q., Frumkin, M., Yan, J.: The OpenMP Implementation of NAS Parallel Benchmarks and its Performance (1999) Bornat, R., Calcagno, C., O’Hearn, P., Parkinson, M.: Permission accounting in separation logic. In: POPL, pp. 259–270 (2005) OpenMP architecture review board, OpenMP API specification for parallel programming. Last accessed 18 Oct 2016. http://openmp.org/wp BotinčanMDoddsMJagannathanSProof-directed parallelization synthesis by separation logicACM Trans. Program. Lang. Syst.20133516010.1145/2491522.2491525 J Smans (601_CR25) 2012; 34 601_CR6 M Dodds (601_CR14) 2016; 38 601_CR5 601_CR3 601_CR2 601_CR1 601_CR21 601_CR22 601_CR20 M Botinčan (601_CR8) 2013; 35 601_CR26 601_CR23 601_CR24 601_CR27 601_CR10 601_CR9 601_CR11 601_CR7 601_CR15 601_CR12 601_CR13 MJ Berger (601_CR4) 2005; 65 601_CR18 601_CR19 601_CR16 601_CR17
References_xml	– reference: LLNL OpenMP Benchmarks. Last accessed 28 Nov 2016. https://asc.llnl.gov/CORAL-benchmarks/ – reference: Bornat, R., Calcagno, C., O’Hearn, P., Parkinson, M.: Permission accounting in separation logic. In: POPL, pp. 259–270 (2005) – reference: Barthe, G., Crespo, J.M., Gulwani, S., Kunz, C., Marron, M.: From relational verification to SIMD loop synthesis. In: PPoPP, pp. 123–134 (2013) – reference: Blom, S., Darabi, S., Huisman, M.: Verification of loop parallelisations. In: Egyed, A., Schaefer, I. (eds.) FASE, Volume 9033 of LNCS. Springer, pp. 202–217 (2015) – reference: Che, S., Boyer, M., Meng, J., Tarjan, D., Sheaffer, J.W., Lee, S.-H., Skadron, K.: Rodinia: A benchmark suite for heterogeneous computing. In Workload Characterization. IISWC 2009, pp. 44–54 (2009) – reference: von Praun, C., Bordawekar, R., Cascaval, C.: Modeling optimistic concurrency using quantitative dependence analysis. In: Proceedings of the 13th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, pp. 185–196 (2008) – reference: Amighi, A., Haack, C., Huisman, M., Hurlin, C.: Permission-based separation logic for multithreaded Java programs. LMCS 11(1), (2015) – reference: Müller, P., Schwerhoff, M., Summers, A.: Viper—a verification infrastructure for permission-based reasoning. In VMCAI (2016) – reference: Leavens, G., Poll, E., Clifton, C., Cheon, Y., Ruby, C., Cok, D.R., Müller, P., Kiniry, J., Chalin, P.: JML Reference Manual (2007). Dept. of Computer Science, Iowa State University. http://www.jmlspecs.org – reference: BergerMJAftosmisMJMarshallDDMurmanSMPerformance of a new CFD flow solver using a hybrid programming paradigmJ. Parallel Distrib. Comput.200565441442310.1016/j.jpdc.2004.11.010 – reference: OpenMP architecture review board, OpenMP API specification for parallel programming. Last accessed 18 Oct 2016. http://openmp.org/wp/ – reference: Aviram, A., Ford, B.: Deterministic OpenMP for Race-free Parallelism. In HotPar’11 (2011) – reference: Bubel, R., Hähnle, R., Heydari Tabar, A.: A program logic for dependence analysis. In: Ahrendt, W., Tapia Tarifa, S.L. (eds.) Integrated Formal Methods. Springer International Publishing, Cham, pp. 83–100 (2019) – reference: SmansJJacobsBPiessensFImplicit dynamic framesACM Trans. Program. Lang. Syst.20123412:12:5810.1145/2160910.2160911 – reference: Haack, C., Huisman, M., Hurlin, C.: Reasoning about Java’s reentrant locks. In: Ramalingam, G., (ed.) Programming Languages and Systems, 6th Asian Symposium, APLAS 2008, Bangalore, India, December 9–11, 2008. Proceedings, Volume 5356 of LNCS. Springer, pp. 171–187 (2008) – reference: Raychev, V., Vechev, M., Yahav, E.: Automatic synthesis of deterministic concurrency. In: Static Analysis—20th International Symposium, SAS 2013, Seattle, WA, USA, June 20–22, 2013. Proceedings. Springer, pp. 283–303 (2013) – reference: Darabi, S., Blom, S., Huisman, M.: A verification technique for deterministic parallel programs. In: Barrett, C., Davies, M., Kahsai, T. (eds.) NASA Formal Methods (NFM), Volume 10227 of LNCS, pp. 247–264 (2017) – reference: Viper project website. http://www.pm.inf.ethz.ch/research/viper – reference: Parkinson, M., Summers, A.: The relationship between separation logic and implicit dynamic frames. In Barthe, G. (ed.) Programming Languages and Systems—20th European Symposium on Programming, ESOP 2011, Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2011, Saarbrücken, Germany, March 26–April 3, 2011. Proceedings, volume 6602 of LNCS. Springer, pp. 439–458 (2011) – reference: Jin, H.-Q., Frumkin, M., Yan, J.: The OpenMP Implementation of NAS Parallel Benchmarks and its Performance (1999) – reference: Botincan, M., Dodds, M., Jagannathan, S.: Resource-sensitive synchronization inference by abduction. In: Field, J., Hicks, M. (eds.) Principles of Programming Languages (POPL 2012), pp. 309–322 (2012) – reference: DoddsMJagannathanSParkinsonMJSvendsenKBirkedalLVerifying custom synchronization constructs using higher-order separation logicACM Trans. Program. Lang. Syst.20163824:14:7210.1145/2818638 – reference: Hurlin, C.: Specification and Verification of Multithreaded Object-Oriented Programs with Separation Logic. PhD thesis, Université Nice Sophia Antipolis (2009) – reference: BotinčanMDoddsMJagannathanSProof-directed parallelization synthesis by separation logicACM Trans. Program. Lang. Syst.20133516010.1145/2491522.2491525 – reference: Boyland, J.: Checking interference with fractional permissions. In: SAS, Volume 2694 of LNCS. Springer, pp. 55–72 (2003) – reference: Salamanca, J., Mattos, L., Araujo, G.: Loop-carried dependence verification in OpenMP. In: International Workshop on OpenMP 2014, pp. 87–102 (2014) – reference: Dodds, M., Jagannathan, S., Parkinson, M.J.: Modular reasoning for deterministic parallelism. In ACM SIGPLAN Notices, pp. 259–270 (2011) – ident: 601_CR1 doi: 10.2168/LMCS-11(1:2)2015 – ident: 601_CR17 – volume: 35 start-page: 1 year: 2013 ident: 601_CR8 publication-title: ACM Trans. Program. Lang. Syst. doi: 10.1145/2491522.2491525 – ident: 601_CR13 doi: 10.1145/1925844.1926416 – ident: 601_CR3 doi: 10.1145/2517327.2442529 – volume: 65 start-page: 414 issue: 4 year: 2005 ident: 601_CR4 publication-title: J. Parallel Distrib. Comput. doi: 10.1016/j.jpdc.2004.11.010 – volume: 38 start-page: 4:1 issue: 2 year: 2016 ident: 601_CR14 publication-title: ACM Trans. Program. Lang. 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Snippet	A commonly used approach to develop deterministic parallel programs is to augment a sequential program with compiler directives that indicate which program...
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StartPage	741
SubjectTerms	Compilers Composition Computer Science Parallel programming Programming languages Representations Semantics Software Software Engineering Software Engineering/Programming and Operating Systems Syntax Theory of Computation Verification
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Title	Correct program parallelisations
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Volume	23
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