ControlPULP: A RISC-V On-Chip Parallel Power Controller for Many-Core HPC Processors with FPGA-Based Hardware-In-The-Loop Power and Thermal Emulation

High-performance computing (HPC) processors are nowadays integrated cyber-physical systems demanding complex and high-bandwidth closed-loop power and thermal control strategies. To efficiently satisfy real-time multi-input multi-output (MIMO) optimal power requirements, high-end processors integrate...

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Published in:	International journal of parallel programming Vol. 52; no. 1-2; pp. 93 - 123
Main Authors:	Ottaviano, Alessandro, Balas, Robert, Bambini, Giovanni, Del Vecchio, Antonio, Ciani, Maicol, Rossi, Davide, Benini, Luca, Bartolini, Andrea
Format:	Journal Article
Language:	English
Published:	New York Springer US 01.04.2024 Springer Nature B.V
Subjects:	Algorithms Closed loops Clusters Computer Science Control algorithms Control theory Controllers Cyber-physical systems Field programmable gate arrays Hardware-in-the-loop simulation Microprocessors MIMO (control systems) Power control Power management Processor Architectures Reactive power Real time RISC Software Engineering/Programming and Operating Systems Theory of Computation Thermal design RISC-V HPC processor PULP Power and thermal control Scalable Parallel microcontroller
ISSN:	0885-7458, 1573-7640
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Abstract	High-performance computing (HPC) processors are nowadays integrated cyber-physical systems demanding complex and high-bandwidth closed-loop power and thermal control strategies. To efficiently satisfy real-time multi-input multi-output (MIMO) optimal power requirements, high-end processors integrate an on-die power controller system (PCS). While traditional PCSs are based on a simple microcontroller (MCU)-class core, more scalable and flexible PCS architectures are required to support advanced MIMO control algorithms for managing the ever-increasing number of cores, power states, and process, voltage, and temperature variability. This paper presents ControlPULP, an open-source, HW/SW RISC-V parallel PCS platform consisting of a single-core MCU with fast interrupt handling coupled with a scalable multi-core programmable cluster accelerator and a specialized DMA engine for the parallel acceleration of real-time power management policies. ControlPULP relies on FreeRTOS to schedule a reactive power control firmware (PCF) application layer. We demonstrate ControlPULP in a power management use-case targeting a next-generation 72-core HPC processor. We first show that the multi-core cluster accelerates the PCF, achieving 4.9x speedup compared to single-core execution, enabling more advanced power management algorithms within the control hyper-period at a shallow area overhead, about 0.1% the area of a modern HPC CPU die. We then assess the PCS and PCF by designing an FPGA-based, closed-loop emulation framework that leverages the heterogeneous SoCs paradigm, achieving DVFS tracking with a mean deviation within 3% the plant’s thermal design power (TDP) against a software-equivalent model-in-the-loop approach. Finally, we show that the proposed PCF compares favorably with an industry-grade control algorithm under computational-intensive workloads.
AbstractList	High-performance computing (HPC) processors are nowadays integrated cyber-physical systems demanding complex and high-bandwidth closed-loop power and thermal control strategies. To efficiently satisfy real-time multi-input multi-output (MIMO) optimal power requirements, high-end processors integrate an on-die power controller system (PCS). While traditional PCSs are based on a simple microcontroller (MCU)-class core, more scalable and flexible PCS architectures are required to support advanced MIMO control algorithms for managing the ever-increasing number of cores, power states, and process, voltage, and temperature variability. This paper presents ControlPULP, an open-source, HW/SW RISC-V parallel PCS platform consisting of a single-core MCU with fast interrupt handling coupled with a scalable multi-core programmable cluster accelerator and a specialized DMA engine for the parallel acceleration of real-time power management policies. ControlPULP relies on FreeRTOS to schedule a reactive power control firmware (PCF) application layer. We demonstrate ControlPULP in a power management use-case targeting a next-generation 72-core HPC processor. We first show that the multi-core cluster accelerates the PCF, achieving 4.9x speedup compared to single-core execution, enabling more advanced power management algorithms within the control hyper-period at a shallow area overhead, about 0.1% the area of a modern HPC CPU die. We then assess the PCS and PCF by designing an FPGA-based, closed-loop emulation framework that leverages the heterogeneous SoCs paradigm, achieving DVFS tracking with a mean deviation within 3% the plant’s thermal design power (TDP) against a software-equivalent model-in-the-loop approach. Finally, we show that the proposed PCF compares favorably with an industry-grade control algorithm under computational-intensive workloads.
Author	Balas, Robert Ciani, Maicol Del Vecchio, Antonio Bartolini, Andrea Benini, Luca Ottaviano, Alessandro Bambini, Giovanni Rossi, Davide
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Cites_doi	10.1109/JSSC.2018.2873584 10.1109/TPDS.2022.3189390 10.1126/science.aam9744 10.1016/j.conengprac.2022.105099 10.1109/MM.2012.12 10.1109/TPDS.2012.117 10.1109/JIOT.2021.3125885 10.1007/978-3-031-15074-6_8 10.1007/978-3-319-67630-2_21 10.1002/spe.v40:11 10.1109/TPDS.2021.3101764 10.1109/TC.2012.293 10.1109/CCTA49430.2022.9966082 10.1145/1454115.1454128 10.1109/HPCS48598.2019.9188239 10.1145/1146909.1147068 10.1109/ISLPED.2015.7273505 10.1109/HOTCHIPS.2015.7477325 10.1109/QRS-C.2019.00047 10.1007/978-3-540-75664-4_16 10.1109/ICCD50377.2020.00067 10.1109/PATMOS.2013.6662161 10.1007/978-0-387-09766-4_370 10.1145/1815961.1815999 10.48550/ARXIV.2205.03725 10.1145/2597917.2597922
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SubjectTerms	Algorithms Closed loops Clusters Computer Science Control algorithms Control theory Controllers Cyber-physical systems Field programmable gate arrays Hardware-in-the-loop simulation Microprocessors MIMO (control systems) Power control Power management Processor Architectures Reactive power Real time RISC Software Engineering/Programming and Operating Systems Theory of Computation Thermal design
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Title	ControlPULP: A RISC-V On-Chip Parallel Power Controller for Many-Core HPC Processors with FPGA-Based Hardware-In-The-Loop Power and Thermal Emulation
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