Buffer Optimization in Network-on-Chip Through Flow Regulation

For network-on-chip (NoC) designs, optimizing buffers is an essential task since buffers are a major source of cost and power consumption. This paper proposes flow regulation and has defined a regulation spectrum as a means for system-on-chip architects to control delay and backlog bounds. The regul...

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Veröffentlicht in:IEEE transactions on computer-aided design of integrated circuits and systems Jg. 29; H. 12; S. 1973 - 1986
Hauptverfasser: Jafari, F, Zhonghai Lu, Jantsch, A, Yaghmaee, M H
Format: Journal Article
Sprache:Englisch
Veröffentlicht: New York IEEE 01.12.2010
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Schlagworte:
Adaptation model
Buffer size
buffer variance
Buffers
Control
Control systems
Delay
Design engineering
Electrical engineering, electronics and photonics
Electronics
Elektronik
Elektroteknik, elektronik och fotonik
interior point method
Minimization
network-on-chip (NoC)
Optimization
Optimization algorithms
optimization problem
Packet switching
Power demand
Reduction
Regulation
Run time (computers)
Studies
System-on-a-chip
TECHNOLOGY
TEKNIKVETENSKAP
Variance
ISSN:0278-0070, 1937-4151, 1937-4151
Online-Zugang:Volltext
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Beschreibung
Zusammenfassung:For network-on-chip (NoC) designs, optimizing buffers is an essential task since buffers are a major source of cost and power consumption. This paper proposes flow regulation and has defined a regulation spectrum as a means for system-on-chip architects to control delay and backlog bounds. The regulation is performed per flow for its peak rate and burstiness. However, many flows may have conflicting regulation requirements due to interferences with each other. Based on the regulation spectrum, this paper optimizes the regulation parameters aiming for buffer optimization. Three timing-constrained buffer optimization problems are formulated, namely, buffer size minimization, buffer variance minimization, and multiobjective optimization, which has both buffer size and variance as minimization objectives. Minimizing buffer variance is also important because it affects the modularity of routers and network interfaces. A realistic case study exhibits 62.8% reduction of total buffers, 84.3% reduction of total latency, and 94.4% reduction on the sum of variances of buffers. Likewise, the experimental results demonstrate similar improvements in the case of synthetic traffic patterns. The optimization algorithm has low run-time complexity, enabling quick exploration of large design spaces. This paper concludes that optimal flow regulation can be a highly valuable instrument for buffer optimization in NoC designs.
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ISSN:0278-0070
1937-4151
1937-4151
DOI:10.1109/TCAD.2010.2063130