Buffer Optimization in Network-on-Chip Through Flow Regulation

For network-on-chip (NoC) designs, optimizing buffers is an essential task since buffers are a major source of cost and power consumption. This paper proposes flow regulation and has defined a regulation spectrum as a means for system-on-chip architects to control delay and backlog bounds. The regul...

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Bibliographic Details
Published in:	IEEE transactions on computer-aided design of integrated circuits and systems Vol. 29; no. 12; pp. 1973 - 1986
Main Authors:	Jafari, F, Zhonghai Lu, Jantsch, A, Yaghmaee, M H
Format:	Journal Article
Language:	English
Published:	New York IEEE 01.12.2010 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:	Adaptation model Buffer size buffer variance Buffers Control Control systems Delay Design engineering Electrical engineering, electronics and photonics Electronics Elektronik Elektroteknik, elektronik och fotonik interior point method Minimization network-on-chip (NoC) Optimization Optimization algorithms optimization problem Packet switching Power demand Reduction Regulation Run time (computers) Studies System-on-a-chip TECHNOLOGY TEKNIKVETENSKAP Variance
ISSN:	0278-0070, 1937-4151, 1937-4151
Online Access:	Get full text
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