Safieh, M., & Freudenberger, J. (2019). Efficient VLSI architecture for the parallel dictionary LZW data compression algorithm. IET circuits, devices & systems, 13(5), 576-583. https://doi.org/10.1049/iet-cds.2018.5017
Citace podle Chicago (17th ed.)Safieh, Malek, a Jürgen Freudenberger. "Efficient VLSI Architecture for the Parallel Dictionary LZW Data Compression Algorithm." IET Circuits, Devices & Systems 13, no. 5 (2019): 576-583. https://doi.org/10.1049/iet-cds.2018.5017.
Citace podle MLA (9th ed.)Safieh, Malek, a Jürgen Freudenberger. "Efficient VLSI Architecture for the Parallel Dictionary LZW Data Compression Algorithm." IET Circuits, Devices & Systems, vol. 13, no. 5, 2019, pp. 576-583, https://doi.org/10.1049/iet-cds.2018.5017.
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