Design of Radix-8 Unsigned Bit Pair Recoding Algorithm-Based Floating-Point Multiplier for Neural Network Computations

The neural network computations for Artificial Intelligence (AI) applications demand high speed, low power and area-efficient Floating-Point (FP) multiplication. In this work, we propose an efficient unsigned Bit Pair Recoding (BPR) algorithm for area, power, and speed improved FP unsigned mantissa...

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Vydané v:	IEEE access Ročník 13; s. 63969 - 63980
Hlavní autori:	Nesam, J. Jean Jenifer, Ganesh, S. Sankar
Médium:	Journal Article
Jazyk:	English
Vydavateľské údaje:	Piscataway IEEE 2025 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Predmet:	Adders Algorithms Area efficient multiplier Artificial intelligence Artificial neural networks bit pair recoding (BPR) algorithm booth encoding algorithm Coding Complexity theory Decoding Delays Encoding error analysis fast multiplication Floating point arithmetic Image coding low power multiplier Multiplication Multipliers multipliers for neural networks Neural networks partial product reduction Power management Resists
ISSN:	2169-3536, 2169-3536
On-line prístup:	Získať plný text
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