ASM GaN: Industry Standard Model for GaN RF and Power Devices-Part-II: Modeling of Charge Trapping

Because of charge trapping in GaN HEMTs, dc characteristics of these devices are not representative of high-frequency operation. The advanced spice model GaN model presented in Part I of this paper is combined with a Shockley-Reed-Hall-based trap model, yielding a comprehensive FET model for GaN HEM...

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Vydáno v:IEEE transactions on electron devices Ročník 66; číslo 1; s. 87 - 94
Hlavní autoři: Albahrani, Sayed Ali, Mahajan, Dhawal, Hodges, Jason, Chauhan, Yogesh Singh, Khandelwal, Sourabh
Médium: Journal Article
Jazyk:angličtina
Vydáno: New York IEEE 01.01.2019
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Témata:
Advanced spice model (ASM) GaN model
compact models
Distance measurement
Electric potential
Electronic devices
Gallium nitride
GaN HEMT
HEMTs
High electron mobility transistors
Industry standards
Integrated circuit modeling
Logic gates
microwave FET
physics-based models
Pulse measurements
semiconductor device measurement
semiconductor device modeling
Semiconductor devices
Trapping
Voltage measurement
ISSN:0018-9383, 1557-9646
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Shrnutí:Because of charge trapping in GaN HEMTs, dc characteristics of these devices are not representative of high-frequency operation. The advanced spice model GaN model presented in Part I of this paper is combined with a Shockley-Reed-Hall-based trap model, yielding a comprehensive FET model for GaN HEMTs which can accurately model GaN devices exhibiting trapping-related dispersion effects. Measurement results of the dc and pulsed output and transfer characteristics of a commercially available GaN HEMT are presented, trapping in the device is modeled, and excellent fit to the measured data is shown. This paper presents an accurate model of trapping which is validated for eight different quiescent bias points of pulse measurements, with quiescent drain voltage ranging from 5 to 20 V and quiescent gate voltage ranging from -2.8 to -3.8 V, and a large range of gate and drain voltages to which the device was pulsed in the pulse measurements and at which the device was measured in the dc measurements, with gate voltage ranging from -4 to 0.4 V and drain voltage ranging from 0 to 40 V. This paper also presents high-frequency (10 GHz) large-signal RF validation of the model for optimal complex load condition.
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ISSN:0018-9383
1557-9646
DOI:10.1109/TED.2018.2868261