An FPGA Design with High Memory Efficiency and Decoding Performance for 5G LDPC Decoder

A hardware-efficient implementation of a Low-Density Parity-Check (LDPC) decoder is presented in this paper. The proposed decoder design is based on the Hybrid Offset Min-Sum (HOMS) algorithm. In the check node processing of this decoder, only the first minimum is computed instead of the first two m...

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Bibliographic Details
Published in:	Electronics (Basel) Vol. 12; no. 17; p. 3667
Main Authors:	Tran-Thi, Bich Ngoc, Nguyen-Ly, Thien Truong, Hoang, Trang
Format:	Journal Article
Language:	English
Published:	Basel MDPI AG 01.09.2023
Subjects:	Algorithms Architecture Circuit design Codes Coding theory Decoders Decoding Design Design and construction Digital integrated circuits Efficiency Error correcting codes Error correction & detection Field programmable gate arrays Hardware Low density parity check codes Methods Parity Random variables Scheduling Vietnam
ISSN:	2079-9292, 2079-9292
Online Access:	Get full text
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