An FPGA Design with High Memory Efficiency and Decoding Performance for 5G LDPC Decoder

A hardware-efficient implementation of a Low-Density Parity-Check (LDPC) decoder is presented in this paper. The proposed decoder design is based on the Hybrid Offset Min-Sum (HOMS) algorithm. In the check node processing of this decoder, only the first minimum is computed instead of the first two m...

Ausführliche Beschreibung

Gespeichert in:

Bibliographische Detailangaben
Veröffentlicht in:	Electronics (Basel) Jg. 12; H. 17; S. 3667
Hauptverfasser:	Tran-Thi, Bich Ngoc, Nguyen-Ly, Thien Truong, Hoang, Trang
Format:	Journal Article
Sprache:	Englisch
Veröffentlicht:	Basel MDPI AG 01.09.2023
Schlagworte:	Algorithms Architecture Circuit design Codes Coding theory Decoders Decoding Design Design and construction Digital integrated circuits Efficiency Error correcting codes Error correction & detection Field programmable gate arrays Hardware Low density parity check codes Methods Parity Random variables Scheduling Vietnam
ISSN:	2079-9292, 2079-9292
Online-Zugang:	Volltext
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!

Abstract	A hardware-efficient implementation of a Low-Density Parity-Check (LDPC) decoder is presented in this paper. The proposed decoder design is based on the Hybrid Offset Min-Sum (HOMS) algorithm. In the check node processing of this decoder, only the first minimum is computed instead of the first two minimum values among all the variable-to-check message inputs as in the conventional approach. Additionally, taking advantage of the unique structure of 5G LDPC codes, layered scheduling and partially parallel structures are employed to minimize hardware costs. Implementation results on the Xilinx Kintex UltraScale+ FPGA platform show that the proposed decoder can achieve a throughput of 2.82 Gbps for 10 decoding iterations with a 5G LDPC codelength of 8832 bits and a code rate of 1/2. Moreover, it yields a check node memory reduction of 10% with respect to the baseline and provides a hardware usage efficiency of 4.96 hardware resources/layer/Mbps, while providing a decoding performance of 0.15 dB better than some of the existing decoders.
AbstractList	A hardware-efficient implementation of a Low-Density Parity-Check (LDPC) decoder is presented in this paper. The proposed decoder design is based on the Hybrid Offset Min-Sum (HOMS) algorithm. In the check node processing of this decoder, only the first minimum is computed instead of the first two minimum values among all the variable-to-check message inputs as in the conventional approach. Additionally, taking advantage of the unique structure of 5G LDPC codes, layered scheduling and partially parallel structures are employed to minimize hardware costs. Implementation results on the Xilinx Kintex UltraScale+ FPGA platform show that the proposed decoder can achieve a throughput of 2.82 Gbps for 10 decoding iterations with a 5G LDPC codelength of 8832 bits and a code rate of 1/2. Moreover, it yields a check node memory reduction of 10% with respect to the baseline and provides a hardware usage efficiency of 4.96 hardware resources/layer/Mbps, while providing a decoding performance of 0.15 dB better than some of the existing decoders.
Audience	Academic
Author	Tran-Thi, Bich Ngoc Nguyen-Ly, Thien Truong Hoang, Trang
Author_xml	– sequence: 1 givenname: Bich Ngoc orcidid: 0000-0001-7942-7995 surname: Tran-Thi fullname: Tran-Thi, Bich Ngoc – sequence: 2 givenname: Thien Truong orcidid: 0000-0002-7422-4600 surname: Nguyen-Ly fullname: Nguyen-Ly, Thien Truong – sequence: 3 givenname: Trang surname: Hoang fullname: Hoang, Trang
BookMark	eNp9kE1LAzEQhoMoWGt_gZeA59Z87Gab49JPoWJBweOSTSZtSjep2S3Sf2-kHkTEmcO8DO8zA-8NuvTBA0J3lIw4l-QB9qC7GLzTLWW04EIUF6jHSCGHkkl2-UNfo0Hb7kgqSfmYkx56Kz2erxclnkLrNh5_uG6Ll26zxU_QhHjCM2udduD1CStvkk0H4_wGryHaEBvlNeAkcL7Aq-l6cjZAvEVXVu1bGHzPPnqZz14ny-HqefE4KVdDzQXthnWtMyXGnDLFSG5rQq0BaYgyEmydAwUpQBtpTJ4ZbgjR49pQBZlmnCreR_fnq4cY3o_QdtUuHKNPDys2FozzTBYiuUZn10btoXLehi4qndpA43QK07q0LwuRMZFTyRIgz4COoW0j2Eq7TnUu-AS6fUVJ9ZV89UfyieW_2EN0jYqnf6lP0iWMUg
CitedBy_id	crossref_primary_10_1002_itl2_539 crossref_primary_10_3390_info15110684 crossref_primary_10_1016_j_compeleceng_2025_110406 crossref_primary_10_3390_computers13080195 crossref_primary_10_1002_dac_5954 crossref_primary_10_3390_technologies12110215 crossref_primary_10_1109_TCSI_2024_3389040
Cites_doi	10.1109/TCE.2010.5506007 10.3390/electronics12051210 10.1109/MCOM.2018.1700839 10.1109/TCSI.2020.3038887 10.1109/4234.905935 10.1109/TIT.2004.831841 10.1109/TCSI.2018.2884252 10.1109/TCSI.2008.924892 10.5370/JEET.2017.12.3.1262 10.1109/TIT.1962.1057683 10.1109/TIT.1981.1056404 10.3390/electronics11050733 10.1109/ISEE51682.2021.9418782 10.1007/s00034-019-01107-z 10.1109/JSSC.2007.916610 10.1109/TVT.2022.3203802 10.1109/TCOMM.2005.852852 10.1109/26.768759 10.1109/18.910572 10.1049/el:19970362 10.1109/TCSI.2020.3018048 10.3390/s22093508 10.1109/TVLSI.2021.3072866 10.1109/26.990903 10.1109/18.910577 10.3390/electronics10040516 10.1109/TSP.2009.2022919
ContentType	Journal Article
Copyright	COPYRIGHT 2023 MDPI AG 2023 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https://creativecommons.org/licenses/by/4.0/). Notwithstanding the ProQuest Terms and Conditions, you may use this content in accordance with the terms of the License.
Copyright_xml	– notice: COPYRIGHT 2023 MDPI AG – notice: 2023 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https://creativecommons.org/licenses/by/4.0/). Notwithstanding the ProQuest Terms and Conditions, you may use this content in accordance with the terms of the License.
DBID	AAYXX CITATION 7SP 8FD 8FE 8FG ABUWG AFKRA ARAPS AZQEC BENPR BGLVJ CCPQU DWQXO HCIFZ L7M P5Z P62 PHGZM PHGZT PIMPY PKEHL PQEST PQGLB PQQKQ PQUKI
DOI	10.3390/electronics12173667
DatabaseName	CrossRef Electronics & Communications Abstracts Technology Research Database ProQuest SciTech Collection ProQuest Technology Collection ProQuest Central (Alumni) ProQuest Central UK/Ireland ProQuest SciTech Premium Collection Technology Collection Advanced Technologies & Aerospace Collection ProQuest Central Essentials - QC ProQuest Central ProQuest Technology Collection ProQuest One ProQuest Central SciTech Premium Collection Advanced Technologies Database with Aerospace Advanced Technologies & Aerospace Database ProQuest Advanced Technologies & Aerospace Collection ProQuest Central Premium ProQuest One Academic (New) ProQuest Publicly Available Content Database ProQuest One Academic Middle East (New) ProQuest One Academic Eastern Edition (DO NOT USE) ProQuest One Applied & Life Sciences ProQuest One Academic (retired) ProQuest One Academic UKI Edition
DatabaseTitle	CrossRef Publicly Available Content Database Advanced Technologies & Aerospace Collection Technology Collection Technology Research Database ProQuest One Academic Middle East (New) ProQuest Advanced Technologies & Aerospace Collection ProQuest Central Essentials ProQuest One Academic Eastern Edition Electronics & Communications Abstracts ProQuest Central (Alumni Edition) SciTech Premium Collection ProQuest One Community College ProQuest Technology Collection ProQuest SciTech Collection ProQuest Central Advanced Technologies & Aerospace Database ProQuest One Applied & Life Sciences ProQuest One Academic UKI Edition ProQuest Central Korea ProQuest Central (New) ProQuest One Academic Advanced Technologies Database with Aerospace ProQuest One Academic (New)
DatabaseTitleList	Publicly Available Content Database CrossRef
Database_xml	– sequence: 1 dbid: PIMPY name: Publicly Available Content Database url: http://search.proquest.com/publiccontent sourceTypes: Aggregation Database
DeliveryMethod	fulltext_linktorsrc
Discipline	Engineering Architecture
EISSN	2079-9292
ExternalDocumentID	A764265192 10_3390_electronics12173667
GeographicLocations	Vietnam
GeographicLocations_xml	– name: Vietnam
GroupedDBID	5VS 8FE 8FG AAYXX ADMLS AFFHD AFKRA ALMA_UNASSIGNED_HOLDINGS ARAPS BENPR BGLVJ CCPQU CITATION HCIFZ IAO ITC KQ8 MODMG M~E OK1 P62 PHGZM PHGZT PIMPY PQGLB PROAC 7SP 8FD ABUWG AZQEC DWQXO L7M PKEHL PQEST PQQKQ PQUKI
ID	FETCH-LOGICAL-c361t-bbc4a68312a205fb01fde9d0ad9efb5e1e96ecd9dd54d3d00c8bd1ae4c231a3
IEDL.DBID	P5Z
ISICitedReferencesCount	8
ISICitedReferencesURI	http://www.webofscience.com/api/gateway?GWVersion=2&SrcApp=Summon&SrcAuth=ProQuest&DestLinkType=CitingArticles&DestApp=WOS_CPL&KeyUT=001063709100001&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D
ISSN	2079-9292
IngestDate	Sun Jul 13 02:52:10 EDT 2025 Tue Nov 04 18:34:10 EST 2025 Sat Nov 29 07:13:21 EST 2025 Tue Nov 18 21:57:09 EST 2025
IsDoiOpenAccess	true
IsOpenAccess	true
IsPeerReviewed	true
IsScholarly	true
Issue	17
Language	English
LinkModel	DirectLink
MergedId	FETCHMERGED-LOGICAL-c361t-bbc4a68312a205fb01fde9d0ad9efb5e1e96ecd9dd54d3d00c8bd1ae4c231a3
Notes	ObjectType-Article-1 SourceType-Scholarly Journals-1 ObjectType-Feature-2 content type line 14
ORCID	0000-0002-7422-4600 0000-0001-7942-7995
OpenAccessLink	https://www.proquest.com/docview/2862334976?pq-origsite=%requestingapplication%
PQID	2862334976
PQPubID	2032404
ParticipantIDs	proquest_journals_2862334976 gale_infotracacademiconefile_A764265192 crossref_citationtrail_10_3390_electronics12173667 crossref_primary_10_3390_electronics12173667
PublicationCentury	2000
PublicationDate	2023-09-01
PublicationDateYYYYMMDD	2023-09-01
PublicationDate_xml	– month: 09 year: 2023 text: 2023-09-01 day: 01
PublicationDecade	2020
PublicationPlace	Basel
PublicationPlace_xml	– name: Basel
PublicationTitle	Electronics (Basel)
PublicationYear	2023
Publisher	MDPI AG
Publisher_xml	– name: MDPI AG
References	Tanner (ref_24) 1981; 27 Verma (ref_23) 2023; 72 Gallager (ref_1) 1962; 8 Liu (ref_5) 2008; 43 Wey (ref_27) 2008; 55 ref_10 Saranovac (ref_21) 2020; 67 Richardson (ref_11) 2001; 47 Boncalo (ref_20) 2018; 66 Lacruz (ref_17) 2019; 38 ref_16 Chung (ref_2) 2001; 5 Chen (ref_14) 2005; 53 Cohen (ref_8) 2009; 57 Savin (ref_26) 2017; 26 Nadal (ref_28) 2021; 29 MacKay (ref_3) 1997; 33 Fossorier (ref_25) 2004; 50 Chen (ref_15) 2002; 50 Kim (ref_7) 2010; 56 Cui (ref_22) 2020; 68 ref_29 Cho (ref_18) 2017; 12 Kschischang (ref_12) 2001; 47 Hoang (ref_19) 2022; 17 ref_4 Fossorier (ref_13) 1999; 47 ref_6 Richardson (ref_9) 2018; 56
References_xml	– volume: 56 start-page: 820 year: 2010 ident: ref_7 article-title: A novel partially parallel architecture for high-throughput LDPC decoder for DVB-S2 publication-title: IEEE Trans. Consum. Electron. doi: 10.1109/TCE.2010.5506007 – ident: ref_6 doi: 10.3390/electronics12051210 – volume: 56 start-page: 28 year: 2018 ident: ref_9 article-title: Design of low-density parity-check codes for 5G new radio publication-title: IEEE Commun. Mag. doi: 10.1109/MCOM.2018.1700839 – volume: 68 start-page: 879 year: 2020 ident: ref_22 article-title: Design of high performance and area-efficient decoder for 5G LDPC codes publication-title: IEEE Trans. Circuits Syst. I Regul. Pap. doi: 10.1109/TCSI.2020.3038887 – volume: 5 start-page: 58 year: 2001 ident: ref_2 article-title: On the design of low-density parity-check codes within 0.0045 dB of the Shannon limit publication-title: IEEE Commun. Lett. doi: 10.1109/4234.905935 – volume: 50 start-page: 1788 year: 2004 ident: ref_25 article-title: Quasicyclic low-density parity-check codes from circulant permutation matrices publication-title: IEEE Trans. Inf. Theory doi: 10.1109/TIT.2004.831841 – volume: 66 start-page: 1643 year: 2018 ident: ref_20 article-title: Layered LDPC decoders with efficient memory access scheduling and mapping and built-in support for pipeline hazards mitigation publication-title: IEEE Trans. Circuits Syst. I Regul. Pap. doi: 10.1109/TCSI.2018.2884252 – volume: 55 start-page: 3430 year: 2008 ident: ref_27 article-title: Algorithms of finding the first two minimum values and their hardware implementation publication-title: IEEE Trans. Circuits Syst. I Regul. Pap. doi: 10.1109/TCSI.2008.924892 – volume: 12 start-page: 1262 year: 2017 ident: ref_18 article-title: Simplified 2-dimensional scaled min-sum algorithm for LDPC decoder publication-title: J. Electr. Eng. Technol. doi: 10.5370/JEET.2017.12.3.1262 – volume: 8 start-page: 21 year: 1962 ident: ref_1 article-title: Low-density parity-check codes publication-title: IRE Trans. Inf. Theory doi: 10.1109/TIT.1962.1057683 – volume: 27 start-page: 533 year: 1981 ident: ref_24 article-title: A recursive approach to low complexity codes publication-title: IEEE Trans. Inf. Theory doi: 10.1109/TIT.1981.1056404 – ident: ref_4 doi: 10.3390/electronics11050733 – ident: ref_16 doi: 10.1109/ISEE51682.2021.9418782 – volume: 38 start-page: 5068 year: 2019 ident: ref_17 article-title: Second minimum approximation for min-sum decoders suitable for high-rate LDPC codes publication-title: Circuits Syst. Signal Process. doi: 10.1007/s00034-019-01107-z – volume: 43 start-page: 684 year: 2008 ident: ref_5 article-title: An LDPC decoder chip based on self-routing network for IEEE 802.16e applications publication-title: IEEE J. Solid-State Circuits doi: 10.1109/JSSC.2007.916610 – volume: 72 start-page: 66 year: 2023 ident: ref_23 article-title: Low computational-complexity SOMS-algorithm and high-throughput decoder architecture for QC-LDPC codes publication-title: IEEE Trans. Veh. Technol. doi: 10.1109/TVT.2022.3203802 – volume: 53 start-page: 1288 year: 2005 ident: ref_14 article-title: Reduced-complexity decoding of LDPC codes publication-title: IEEE Trans. Commun. doi: 10.1109/TCOMM.2005.852852 – volume: 26 start-page: 508 year: 2017 ident: ref_26 article-title: Analysis and design of cost-effective, high-throughput LDPC decoders publication-title: IEEE Trans. Very Large Scale Integr. VLSI Syst. – volume: 47 start-page: 673 year: 1999 ident: ref_13 article-title: Reduced complexity iterative decoding of low-density parity-check codes based on belief propagation publication-title: IEEE Trans. Commun. doi: 10.1109/26.768759 – volume: 17 start-page: 358 year: 2022 ident: ref_19 article-title: High-performance and low complexity decoding algorithms for 5G Low-Density Parity-Check codes publication-title: J. Commun. – volume: 47 start-page: 498 year: 2001 ident: ref_12 article-title: Factor graphs and the sum-product algorithm publication-title: IEEE Trans. Inf. Theory doi: 10.1109/18.910572 – volume: 33 start-page: 457 year: 1997 ident: ref_3 article-title: Near Shannon limit performance of low-density parity check codes publication-title: Electron. Lett. doi: 10.1049/el:19970362 – volume: 67 start-page: 5454 year: 2020 ident: ref_21 article-title: Flexible high throughput QC-LDPC decoder with perfect pipeline conflicts resolution and efficient hardware utilization publication-title: IEEE Trans. Circuits Syst. I Regul. Pap. doi: 10.1109/TCSI.2020.3018048 – ident: ref_29 doi: 10.3390/s22093508 – volume: 29 start-page: 1141 year: 2021 ident: ref_28 article-title: Parallel and flexible 5G LDPC decoder architecture targeting FPGA publication-title: IEEE Trans. Very Large Scale Integr. VLSI Syst. doi: 10.1109/TVLSI.2021.3072866 – volume: 50 start-page: 406 year: 2002 ident: ref_15 article-title: Near optimum universal belief propagation based decoding of low-density parity check codes publication-title: IEEE Trans. Commun. doi: 10.1109/26.990903 – volume: 47 start-page: 599 year: 2001 ident: ref_11 article-title: The capacity of low-density parity-check codes under message-passing decoding publication-title: IEEE Trans. Inf. Theory doi: 10.1109/18.910577 – ident: ref_10 doi: 10.3390/electronics10040516 – volume: 57 start-page: 4085 year: 2009 ident: ref_8 article-title: A low-complexity hybrid LDPC code encoder for IEEE802.3an (10GBase-T) ethernet publication-title: IEEE Trans. Signal Process. doi: 10.1109/TSP.2009.2022919
SSID	ssj0000913830
Score	2.3111691
Snippet	A hardware-efficient implementation of a Low-Density Parity-Check (LDPC) decoder is presented in this paper. The proposed decoder design is based on the Hybrid...
SourceID	proquest gale crossref
SourceType	Aggregation Database Enrichment Source Index Database
StartPage	3667
SubjectTerms	Algorithms Architecture Circuit design Codes Coding theory Decoders Decoding Design Design and construction Digital integrated circuits Efficiency Error correcting codes Error correction & detection Field programmable gate arrays Hardware Low density parity check codes Methods Parity Random variables Scheduling
Title	An FPGA Design with High Memory Efficiency and Decoding Performance for 5G LDPC Decoder
URI	https://www.proquest.com/docview/2862334976
Volume	12
WOSCitedRecordID	wos001063709100001&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D
hasFullText	1
inHoldings	1
isFullTextHit
isPrint
journalDatabaseRights	– providerCode: PRVHPJ databaseName: ROAD: Directory of Open Access Scholarly Resources customDbUrl: eissn: 2079-9292 dateEnd: 99991231 omitProxy: false ssIdentifier: ssj0000913830 issn: 2079-9292 databaseCode: M~E dateStart: 20120101 isFulltext: true titleUrlDefault: https://road.issn.org providerName: ISSN International Centre – providerCode: PRVPQU databaseName: Advanced Technologies & Aerospace Database customDbUrl: eissn: 2079-9292 dateEnd: 99991231 omitProxy: false ssIdentifier: ssj0000913830 issn: 2079-9292 databaseCode: P5Z dateStart: 20120301 isFulltext: true titleUrlDefault: https://search.proquest.com/hightechjournals providerName: ProQuest – providerCode: PRVPQU databaseName: ProQuest Central customDbUrl: eissn: 2079-9292 dateEnd: 99991231 omitProxy: false ssIdentifier: ssj0000913830 issn: 2079-9292 databaseCode: BENPR dateStart: 20120301 isFulltext: true titleUrlDefault: https://www.proquest.com/central providerName: ProQuest – providerCode: PRVPQU databaseName: Publicly Available Content Database customDbUrl: eissn: 2079-9292 dateEnd: 99991231 omitProxy: false ssIdentifier: ssj0000913830 issn: 2079-9292 databaseCode: PIMPY dateStart: 20120301 isFulltext: true titleUrlDefault: http://search.proquest.com/publiccontent providerName: ProQuest
link	http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwpV1JS8NAFH6o9aCCu1itZQ6CF4OTTNaTxG4KtgQVXC5htoAgqbZV8OJvd16SWg_Si7eQvAnDvJl5y7z5PoBj6hlDqgNqcd-XlhtoZgljxyxhXFk_irRyRMFach0MBuHDQ5RUCbdxVVY53ROLjVoNJebIzxzjejPmGut5_vpmIWsUnq5WFBqLUEOUBKRuSLynnxwLYl6GjJZgQ8xE92czbpmxaRAwv-CXnxmkv7flwtZ0N_7by01Yr7xMEpfTYgsWdL4Na_GvQ4NtWP0FRbgD93FOukkvJu2ipINgfpZgEQjpYy3uJ-kUWBN4UZPwXBkxOUSzR5LZzQNiHojXI9ftpFUK6NEu3HY7d61LqyJdsCTz7YklhHS5HzLb4Q71MkHtTOlIUa4inQlP2zrytVSRUp6rmKJUhkLZXLvSeIqc7cFSPsz1PhBHugjkw3XIMldkTiRolnGMxiWi2vE6ONNxT2WFR460GC-piUtQWekfyqrD6U-j1xKOY774CSo0xcVq_i15defA9BBhr9I4MOGXb5xYpw6NqULTahWP05k2D-Z_PoQVpKEva88asDQZvesjWJYfk-fxqAm1i84guWnCYv-r0yymqHmXXPWTx2-_9vE_
linkProvider	ProQuest
linkToHtml	http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMw1V1Lb9NAEB6VFIlSiUcpIlBgDyAuWF3v2o73UCGradqoSWSJSpQL1r4sISGnJAHU_8SPZMaPpoeqtx64WfLasr2fZ76dnfkG4B2P0ZH6AQ90ktggGngZGPRjgUEqmyjlnTB115LJYDZLz89VvgF_u1oYSqvsbGJtqN3cUox8XyD1ljJC7_np4mdAXaNod7VrodHA4tRf_sEl2_JgPMT5fS_E6Ojs8CRouwoEVibhKjDGRjpJZSi04HFpeFg6rxzXTvnSxD70KvHWKefiyEnHuU2NC7WPLFIhLfGu92AzIqj3YDMfT_OvVzEd0thMJW_EjaRUfH_dy2YZIvmXSd3Pfu0Ab3YDtW8bPf6_vsoTeNRyaJY1oH8KG77age3s2pbIDjy8JrT4DL5kFRvlxxkb1gkrjKLPjFJc2JQyjS_ZUa2kQWWoTFcOh9k5OXWWr-sqGB6w-JhNhvlhM8AvduHzHbzmc-hV88q_ACZsRDJF2qeyjEwplOFlqSnWYEmzT_dBdLNc2FZtnZp-_Chw1UXQKG6ARh8-Xl100YiN3D78A8GnIFOE97a6rajAJyRRryIb4OIyQYou-rDXwadobdSyWGPn5e2n38KDk7PppJiMZ6evYEsgzWuy7Pagt1r88q_hvv29-r5cvGl_CAbf7hZr_wBw0U26
linkToPdf	http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMw1V1LaxRBEC5iImKEqFHJajR9ULw4bE_3vPogMmSzSci6DCgYPDj0a0CQ2bi7ieSf-fOsmkc2h5BbDt4GpqeZmf66Xl31FcBbHqMi9SkPdJLYIEq9DAzqscCgKZso5Z0wTdeSSTqdZqenqliDv30tDKVV9jKxEdRuZilGPhRoeksZofYcVl1aRDEafzr7HVAHKTpp7dtptBA58Zd_0H1bfDwe4Vq_E2J88HX_KOg6DARWJuEyMMZGOslkKLTgcWV4WDmvHNdO-crEPvQq8dYp5-LISce5zYwLtY8smkVa4qz3YCNFD5OSCYv4-1V0h9g2M8lbmiMpFR-uutosQnQDZNJ0tl-pwpsVQqPlxo__3__zBLY6y5rl7VZ4Cmu-3oZH-bWDkm3YvEa_-Ay-5TUbF4c5GzVpLIxi0owSX9hnyj--ZAcNvwYVpzJdOxxmZ6TqWbGqtmB4weJDNhkV--0AP38OX-7gM1_Aej2r_Q4wYSMiL9I-k1VkKqEMrypNEQhLTH56AKJf8dJ2HOzUCuRXib4YwaS8ASYD-HD10FlLQXL78PcEpZIEFM5tdVdngW9IVF9lnqLLmaDhLgaw20Op7CTXolzh6OXtt_fgAQKsnBxPT17BQ4G2X5t6twvry_m5fw337cXy52L-ptkZDH7cLdD-Ab9_VR0
openUrl	ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.atitle=An+FPGA+Design+with+High+Memory+Efficiency+and+Decoding+Performance+for+5G+LDPC+Decoder&rft.jtitle=Electronics+%28Basel%29&rft.au=Tran-Thi%2C+Bich+Ngoc&rft.au=Thien+Truong+Nguyen-Ly&rft.au=Hoang%2C+Trang&rft.date=2023-09-01&rft.pub=MDPI+AG&rft.eissn=2079-9292&rft.volume=12&rft.issue=17&rft.spage=3667&rft_id=info:doi/10.3390%2Felectronics12173667&rft.externalDBID=HAS_PDF_LINK
thumbnail_l	http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/lc.gif&issn=2079-9292&client=summon
thumbnail_m	http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/mc.gif&issn=2079-9292&client=summon
thumbnail_s	http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/sc.gif&issn=2079-9292&client=summon