Tran-Thi, B. N., Nguyen-Ly, T. T., & Hoang, T. (2023). An FPGA Design with High Memory Efficiency and Decoding Performance for 5G LDPC Decoder. Electronics (Basel), 12(17), 3667. https://doi.org/10.3390/electronics12173667
Citace podle Chicago (17th ed.)Tran-Thi, Bich Ngoc, Thien Truong Nguyen-Ly, a Trang Hoang. "An FPGA Design with High Memory Efficiency and Decoding Performance for 5G LDPC Decoder." Electronics (Basel) 12, no. 17 (2023): 3667. https://doi.org/10.3390/electronics12173667.
Citace podle MLA (9th ed.)Tran-Thi, Bich Ngoc, et al. "An FPGA Design with High Memory Efficiency and Decoding Performance for 5G LDPC Decoder." Electronics (Basel), vol. 12, no. 17, 2023, p. 3667, https://doi.org/10.3390/electronics12173667.
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