NN2FPGA: Optimizing CNN Inference on FPGAs With Binary Integer Programming

Skip connections have emerged as a key component of modern convolutional neural networks (CNNs) for computer vision tasks, allowing for the creation of more accurate and deeper models by addressing the vanishing gradient problem. However, the existing implementations of field-programmable gate array...

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Vydané v:	IEEE transactions on computer-aided design of integrated circuits and systems Ročník 44; číslo 5; s. 1807 - 1818
Hlavní autori:	Bosio, Roberto, Minnella, Filippo, Urso, Teodoro, Casu, Mario R., Lavagno, Luciano, Lazarescu, Mihai T., Pasini, Paolo
Médium:	Journal Article
Jazyk:	English
Vydavateľské údaje:	New York IEEE 01.05.2025 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Predmet:	Accelerators Accuracy Artificial neural networks Codesign Compilers Computational modeling Computer vision Convolutional codes Convolutional neural networks dataflow architecture Design of experiments Design optimization Field programmable gate arrays field-programmable gate array (FPGA) acceleration graph optimization High level synthesis Integer programming Machine learning Network latency Optimization pipelining quantization Quantization (signal) residual neural networks (NNs) Resource utilization System-on-chip Throughput
ISSN:	0278-0070, 1937-4151
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Abstract	Skip connections have emerged as a key component of modern convolutional neural networks (CNNs) for computer vision tasks, allowing for the creation of more accurate and deeper models by addressing the vanishing gradient problem. However, the existing implementations of field-programmable gate array (FPGA)-based accelerators for ResNets and MobileNetV2 often experience decreased performance and increased computational latency due to the implementation of skip blocks. This article presents a novel framework for developing deep learning models on FPGAs that focuses on skip connections, with a unique approach to reduce buffering overhead. This results in a more efficient utilization of resources in the implementation of the skip layer. The nn2fpga compiler follows a thorough set of high-level synthesis (HLS) design principles and optimization strategies, exploiting in novel ways standard techniques to effectively map skip connection-based networks into static dataflow accelerators. To maximize throughput and efficiently use the available resources, our compiler employs a fast and effective design space exploration method based on a binary integer programming model which accurately assigns FPGA resources to the network layers, to maximize global throughput under resource constraints and then minimize resources for the achieved maximum throughput. Experimental results on the CIFAR-10 and ImageNet datasets demonstrate substantial gains in throughput (<inline-formula> <tex-math notation="LaTeX">\mathbf {3\times } </tex-math></inline-formula>-<inline-formula> <tex-math notation="LaTeX">\mathbf {7\times } </tex-math></inline-formula> on the past HLS-based work) for ResNet8, ResNet20, and MobileNetV2 models deployed on various Xilinx FPGA boards. Notably, MobileNetV2 deployed on the ZCU102 achieves a throughput of 2115 frame per second, representing even a 10% speedup over a state-of-the-art highly optimized manual register-transfer level implementation, showing that HLS can actually improve over manual design, thanks to the faster exploration of the design space.
AbstractList	Skip connections have emerged as a key component of modern convolutional neural networks (CNNs) for computer vision tasks, allowing for the creation of more accurate and deeper models by addressing the vanishing gradient problem. However, the existing implementations of field-programmable gate array (FPGA)-based accelerators for ResNets and MobileNetV2 often experience decreased performance and increased computational latency due to the implementation of skip blocks. This article presents a novel framework for developing deep learning models on FPGAs that focuses on skip connections, with a unique approach to reduce buffering overhead. This results in a more efficient utilization of resources in the implementation of the skip layer. The nn2fpga compiler follows a thorough set of high-level synthesis (HLS) design principles and optimization strategies, exploiting in novel ways standard techniques to effectively map skip connection-based networks into static dataflow accelerators. To maximize throughput and efficiently use the available resources, our compiler employs a fast and effective design space exploration method based on a binary integer programming model which accurately assigns FPGA resources to the network layers, to maximize global throughput under resource constraints and then minimize resources for the achieved maximum throughput. Experimental results on the CIFAR-10 and ImageNet datasets demonstrate substantial gains in throughput ([Formula Omitted]–[Formula Omitted] on the past HLS-based work) for ResNet8, ResNet20, and MobileNetV2 models deployed on various Xilinx FPGA boards. Notably, MobileNetV2 deployed on the ZCU102 achieves a throughput of 2115 frame per second, representing even a 10% speedup over a state-of-the-art highly optimized manual register-transfer level implementation, showing that HLS can actually improve over manual design, thanks to the faster exploration of the design space. Skip connections have emerged as a key component of modern convolutional neural networks (CNNs) for computer vision tasks, allowing for the creation of more accurate and deeper models by addressing the vanishing gradient problem. However, the existing implementations of field-programmable gate array (FPGA)-based accelerators for ResNets and MobileNetV2 often experience decreased performance and increased computational latency due to the implementation of skip blocks. This article presents a novel framework for developing deep learning models on FPGAs that focuses on skip connections, with a unique approach to reduce buffering overhead. This results in a more efficient utilization of resources in the implementation of the skip layer. The nn2fpga compiler follows a thorough set of high-level synthesis (HLS) design principles and optimization strategies, exploiting in novel ways standard techniques to effectively map skip connection-based networks into static dataflow accelerators. To maximize throughput and efficiently use the available resources, our compiler employs a fast and effective design space exploration method based on a binary integer programming model which accurately assigns FPGA resources to the network layers, to maximize global throughput under resource constraints and then minimize resources for the achieved maximum throughput. Experimental results on the CIFAR-10 and ImageNet datasets demonstrate substantial gains in throughput (<inline-formula> <tex-math notation="LaTeX">\mathbf {3\times } </tex-math></inline-formula>-<inline-formula> <tex-math notation="LaTeX">\mathbf {7\times } </tex-math></inline-formula> on the past HLS-based work) for ResNet8, ResNet20, and MobileNetV2 models deployed on various Xilinx FPGA boards. Notably, MobileNetV2 deployed on the ZCU102 achieves a throughput of 2115 frame per second, representing even a 10% speedup over a state-of-the-art highly optimized manual register-transfer level implementation, showing that HLS can actually improve over manual design, thanks to the faster exploration of the design space.
Author	Lavagno, Luciano Urso, Teodoro Lazarescu, Mihai T. Casu, Mario R. Pasini, Paolo Bosio, Roberto Minnella, Filippo
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SubjectTerms	Accelerators Accuracy Artificial neural networks Codesign Compilers Computational modeling Computer vision Convolutional codes Convolutional neural networks dataflow architecture Design of experiments Design optimization Field programmable gate arrays field-programmable gate array (FPGA) acceleration graph optimization High level synthesis Integer programming Machine learning Network latency Optimization pipelining quantization Quantization (signal) residual neural networks (NNs) Resource utilization System-on-chip Throughput
Title	NN2FPGA: Optimizing CNN Inference on FPGAs With Binary Integer Programming
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