Fast parallel algorithms for binary multiplication and their implementation on systolic architectures

Two algorithms for parallel multiplication of two n-bit binary numbers are presented. Both use column compression to increase the speed of execution. They require almost regular interconnection between only two types of cells and hence are very suitable for VLSI implementation. Both of them can also...

Full description

Saved in:
Bibliographic Details
Published in:IEEE transactions on computers Vol. 38; no. 3; pp. 424 - 431
Main Authors: Sinha, B.P., Srimani, P.K.
Format: Journal Article
Language:English
Published: New York, NY IEEE 01.03.1989
Institute of Electrical and Electronics Engineers
Subjects:
Adders
Algorithmics. Computability. Computer arithmetics
Applied sciences
Binary trees
Chip scale packaging
Computer architecture
Computer science
Computer science; control theory; systems
Exact sciences and technology
Integrated circuit interconnections
Iterative algorithms
Parallel algorithms
Parallel processing
Theoretical computing
Very large scale integration
Parallel algorithm
Computers arithmetic
VLSI circuit
Computer theory
Integrated circuit
SIMD computer
Fast algorithm
Implementation
Binary multiplier
ISSN:0018-9340
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:Two algorithms for parallel multiplication of two n-bit binary numbers are presented. Both use column compression to increase the speed of execution. They require almost regular interconnection between only two types of cells and hence are very suitable for VLSI implementation. Both of them can also be easily modified to handle two's complement numbers with constant differences in time.< >
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
content type line 23
ISSN:0018-9340
DOI:10.1109/12.21128