APA (7th ed.) Citation

Sinha, B., & Srimani, P. (1989). Fast parallel algorithms for binary multiplication and their implementation on systolic architectures. IEEE transactions on computers, 38(3), 424-431. https://doi.org/10.1109/12.21128

Chicago Style (17th ed.) Citation

Sinha, B.P, and P.K Srimani. "Fast Parallel Algorithms for Binary Multiplication and Their Implementation on Systolic Architectures." IEEE Transactions on Computers 38, no. 3 (1989): 424-431. https://doi.org/10.1109/12.21128.

MLA (9th ed.) Citation

Sinha, B.P, and P.K Srimani. "Fast Parallel Algorithms for Binary Multiplication and Their Implementation on Systolic Architectures." IEEE Transactions on Computers, vol. 38, no. 3, 1989, pp. 424-431, https://doi.org/10.1109/12.21128.