System-on-a-Chip (SoC)-Based Hardware Acceleration for an Online Sequential Extreme Learning Machine (OS-ELM)

Machine learning algorithms such as those for object classification in images, video content analysis, and human action recognition are used to extract meaningful information from data recorded by image sensors and cameras. Among the existing machine learning algorithms for such purposes, extreme le...

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Veröffentlicht in:IEEE transactions on computer-aided design of integrated circuits and systems Jg. 38; H. 11; S. 2127 - 2138
Hauptverfasser: Safaei, Amin, Wu, Q. M. Jonathan, Akilan, Thangarajah, Yang, Yimin
Format: Journal Article
Sprache:Englisch
Veröffentlicht: New York IEEE 01.11.2019
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Schlagworte:
Acceleration
Algorithms
Artificial intelligence
Artificial neural networks
Computer architecture
Content analysis
Embedded systems
Extreme learning machine (ELM)
Field programmable gate arrays
Hardware
hardware (HW)
Human activity recognition
Human motion
Image classification
Machine learning
Machine learning algorithms
Matrix decomposition
neural networks (NNs)
online sequential ELM (OS-ELM)
Pipelining (computers)
Power consumption
System on chip
system-on-a-chip field-programmable gate array (SoC FPGA)
Training
Video data
ISSN:0278-0070, 1937-4151
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Zusammenfassung:Machine learning algorithms such as those for object classification in images, video content analysis, and human action recognition are used to extract meaningful information from data recorded by image sensors and cameras. Among the existing machine learning algorithms for such purposes, extreme learning machines (ELMs) and online sequential ELMs (OS-ELMs) are well known for their computational efficiency and performance when processing large datasets. The latter approach was derived from the ELM approach and optimized for real-time application. However, OS-ELM classifiers are computationally demanding, and the existing state-of-the-art computing platforms are not efficient enough for embedded systems, especially for applications with strict requirements in terms of low power consumption, high throughput, and low latency. This paper presents the implementation of an ELM/OS-ELM in a customized system-on-a-chip field-programmable gate array-based architecture to ensure efficient hardware acceleration. The acceleration process comprises parallel extraction, deep pipelining, and efficient shared memory communication.
Bibliographie:ObjectType-Article-1
SourceType-Scholarly Journals-1
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ISSN:0278-0070
1937-4151
DOI:10.1109/TCAD.2018.2878162