A Scalable CMOS Ising Computer Featuring Sparse and Reconfigurable Spin Interconnects for Solving Combinatorial Optimization Problems

No existing algorithms can find exact solutions to the combinatorial optimization problems (COPs) classified as non-deterministic polynomial-time (NP) hard problems. Alternatively, Ising computer based on the Ising model and annealing process has recently drawn significant attention. The Ising compu...

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Veröffentlicht in:	IEEE journal of solid-state circuits Jg. 57; H. 3; S. 858 - 868
Hauptverfasser:	Su, Yuqi, Mu, Junjie, Kim, Hyunjoon, Kim, Bongjin
Format:	Journal Article
Sprache:	Englisch
Veröffentlicht:	New York IEEE 01.03.2022 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Schlagworte:	Algorithms Annealing Annealing processor CMOS Combinatorial analysis combinatorial optimization problems (COPs) Computational modeling Couplers Exact solutions Hardware Integrated circuit interconnections Interconnections Ising computer Ising model Lattices Mapping minor embedding Optimization Polynomials Qubit Reconfigurable hardware sparse and reconfigurable interconnects Spin dynamics
ISSN:	0018-9200, 1558-173X
Online-Zugang:	Volltext
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