A Scalable CMOS Ising Computer Featuring Sparse and Reconfigurable Spin Interconnects for Solving Combinatorial Optimization Problems

No existing algorithms can find exact solutions to the combinatorial optimization problems (COPs) classified as non-deterministic polynomial-time (NP) hard problems. Alternatively, Ising computer based on the Ising model and annealing process has recently drawn significant attention. The Ising compu...

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Vydané v:IEEE journal of solid-state circuits Ročník 57; číslo 3; s. 858 - 868
Hlavní autori: Su, Yuqi, Mu, Junjie, Kim, Hyunjoon, Kim, Bongjin
Médium: Journal Article
Jazyk:English
Vydavateľské údaje: New York IEEE 01.03.2022
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Predmet:
Algorithms
Annealing
Annealing processor
CMOS
Combinatorial analysis
combinatorial optimization problems (COPs)
Computational modeling
Couplers
Exact solutions
Hardware
Integrated circuit interconnections
Interconnections
Ising computer
Ising model
Lattices
Mapping
minor embedding
Optimization
Polynomials
Qubit
Reconfigurable hardware
sparse and reconfigurable interconnects
Spin dynamics
ISSN:0018-9200, 1558-173X
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Abstract No existing algorithms can find exact solutions to the combinatorial optimization problems (COPs) classified as non-deterministic polynomial-time (NP) hard problems. Alternatively, Ising computer based on the Ising model and annealing process has recently drawn significant attention. The Ising computers can find approximate solutions to the NP-hard COPs by observing the convergence of dynamic spin states. However, they have encountered challenges in mapping the optimization problems to the inflexible Ising computers with fixed spin interconnects. In this article, we propose a scalable CMOS Ising computer with sparse and reconfigurable spin interconnects for arbitrary mapping of spin networks with minimal overhead. Without a mapping algorithm, the proposed Ising computer provides a method for directly mapping COPs to the reconfigurable hardware. A 65-nm CMOS Ising test chip with 252 spins is fabricated and used for solving COPs, including max-cut problems.
AbstractList No existing algorithms can find exact solutions to the combinatorial optimization problems (COPs) classified as non-deterministic polynomial-time (NP) hard problems. Alternatively, Ising computer based on the Ising model and annealing process has recently drawn significant attention. The Ising computers can find approximate solutions to the NP-hard COPs by observing the convergence of dynamic spin states. However, they have encountered challenges in mapping the optimization problems to the inflexible Ising computers with fixed spin interconnects. In this article, we propose a scalable CMOS Ising computer with sparse and reconfigurable spin interconnects for arbitrary mapping of spin networks with minimal overhead. Without a mapping algorithm, the proposed Ising computer provides a method for directly mapping COPs to the reconfigurable hardware. A 65-nm CMOS Ising test chip with 252 spins is fabricated and used for solving COPs, including max-cut problems.
Author Kim, Hyunjoon
Mu, Junjie
Kim, Bongjin
Su, Yuqi
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SubjectTerms Algorithms
Annealing
Annealing processor
CMOS
Combinatorial analysis
combinatorial optimization problems (COPs)
Computational modeling
Couplers
Exact solutions
Hardware
Integrated circuit interconnections
Interconnections
Ising computer
Ising model
Lattices
Mapping
minor embedding
Optimization
Polynomials
Qubit
Reconfigurable hardware
sparse and reconfigurable interconnects
Spin dynamics
Title A Scalable CMOS Ising Computer Featuring Sparse and Reconfigurable Spin Interconnects for Solving Combinatorial Optimization Problems
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