Concatenated LDPC/2-D-Marker Codes and Non-Iterative Detection/Decoding for Recovering Position Errors in Racetrack Memories

Racetrack memories (RMs) are prone to alignment faults called position errors (PEs), which manifest as insertions and deletions of stored data bits. Conventional coding schemes for PEs demonstrate the promising results by employing low-density parity-check (LDPC) codes with an iterative detection an...

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Veröffentlicht in:	IEEE transactions on magnetics Jg. 56; H. 9; S. 1 - 9
Hauptverfasser:	Shibata, Ryo, Hosoya, Gou, Yashima, Hiroyuki
Format:	Journal Article
Sprache:	Englisch
Veröffentlicht:	New York IEEE 01.09.2020 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Schlagworte:	Algorithms Asymptotic properties Binary system Codes Coding Complexity Computer simulation Decoding Detectors Encoding Error correcting codes Iterative decoding Iterative methods Low density parity check codes Low-density parity-check (LDPC) codes Magnetism Markers position error (PE) Position errors racetrack memories (RMs) Reliability synchronization marker Target tracking
ISSN:	0018-9464, 1941-0069
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Abstract	Racetrack memories (RMs) are prone to alignment faults called position errors (PEs), which manifest as insertions and deletions of stored data bits. Conventional coding schemes for PEs demonstrate the promising results by employing low-density parity-check (LDPC) codes with an iterative detection and decoding algorithm. However, the computational complexity of detection is relatively high. In this article, for channels with PEs, we present a new coding scheme that can effectively decode corrupted data, even if the detection is executed only once (i.e., a non-iterative detection and decoding scenario). The proposed code consists of a concatenation of an inner 2-D marker code, which is specialized for PEs to mitigate the effect of insertion and deletion (ID) errors, and an outer irregular LDPC code. We also provide tractable design methodologies for these constituent codes. First, we identify the 2-D-marker code structures that offer higher achievable information rates in a non-iterative scenario and then optimize irregular LDPC codes to ensure good decoding properties. Through asymptotic-performance analysis and finite-length simulation, we confirm the effectiveness of the proposed coding scheme. Ultimately, the proposed coding scheme has the capability to reduce code rate loss and to provide excellent decoding performance under a non-iterative scenario, which also helps in understanding the reliability of RM when a low-complexity decoding algorithm is used to correct ID errors caused by PEs.
AbstractList	Racetrack memories (RMs) are prone to alignment faults called position errors (PEs), which manifest as insertions and deletions of stored data bits. Conventional coding schemes for PEs demonstrate the promising results by employing low-density parity-check (LDPC) codes with an iterative detection and decoding algorithm. However, the computational complexity of detection is relatively high. In this article, for channels with PEs, we present a new coding scheme that can effectively decode corrupted data, even if the detection is executed only once (i.e., a non-iterative detection and decoding scenario). The proposed code consists of a concatenation of an inner 2-D marker code, which is specialized for PEs to mitigate the effect of insertion and deletion (ID) errors, and an outer irregular LDPC code. We also provide tractable design methodologies for these constituent codes. First, we identify the 2-D-marker code structures that offer higher achievable information rates in a non-iterative scenario and then optimize irregular LDPC codes to ensure good decoding properties. Through asymptotic-performance analysis and finite-length simulation, we confirm the effectiveness of the proposed coding scheme. Ultimately, the proposed coding scheme has the capability to reduce code rate loss and to provide excellent decoding performance under a non-iterative scenario, which also helps in understanding the reliability of RM when a low-complexity decoding algorithm is used to correct ID errors caused by PEs.
Author	Hosoya, Gou Yashima, Hiroyuki Shibata, Ryo
Author_xml	– sequence: 1 givenname: Ryo orcidid: 0000-0002-5342-2747 surname: Shibata fullname: Shibata, Ryo email: ryo12049@gmail.com organization: Department of Information and Computer Technology, Faculty of Engineering, Tokyo University of Science, Tokyo, Japan – sequence: 2 givenname: Gou orcidid: 0000-0002-3200-1118 surname: Hosoya fullname: Hosoya, Gou organization: Global Education Center, Waseda University, Tokyo, Japan – sequence: 3 givenname: Hiroyuki orcidid: 0000-0002-1705-2929 surname: Yashima fullname: Yashima, Hiroyuki organization: Department of Information and Computer Technology, Faculty of Engineering, Tokyo University of Science, Tokyo, Japan
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SubjectTerms	Algorithms Asymptotic properties Binary system Codes Coding Complexity Computer simulation Decoding Detectors Encoding Error correcting codes Iterative decoding Iterative methods Low density parity check codes Low-density parity-check (LDPC) codes Magnetism Markers position error (PE) Position errors racetrack memories (RMs) Reliability synchronization marker Target tracking
Title	Concatenated LDPC/2-D-Marker Codes and Non-Iterative Detection/Decoding for Recovering Position Errors in Racetrack Memories
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