Low-Latency Unfolded-KES Architecture for Emerging Storage Class Memories

This paper presents an advanced key-equation solver (KES) algorithm that can reduce the computing latency of BCH decoding for the high-speed storage class memory (SCM). Adopting the unfolding algorithm as a factor of two, compared to the conventional iterative KES scheme, the proposed work potential...

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Vydáno v:IEEE transactions on circuits and systems. I, Regular papers Ročník 67; číslo 6; s. 2103 - 2113
Hlavní autoři: Moon, Seungsik, Choe, Jeongwon, Lee, Youngjoo
Médium: Journal Article
Jazyk:angličtina
Vydáno: New York IEEE 01.06.2020
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Témata:
Acceleration
Algorithms
BCH decoding
Computation
Deactivation
Decoding
Delays
emerging nonvolatile memory
Energy consumption
error-correction code
High speed
Indexes
Iterative decoding
Iterative methods
low-latency processing
Memory management
Modules
Recovery
VLSI
ISSN:1549-8328, 1558-0806
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Shrnutí:This paper presents an advanced key-equation solver (KES) algorithm that can reduce the computing latency of BCH decoding for the high-speed storage class memory (SCM). Adopting the unfolding algorithm as a factor of two, compared to the conventional iterative KES scheme, the proposed work potentially halves the number of processing cycles for KES module, which is normally dominates the overall BCH decoding latency. In contrast that the straight-forward unfolding method increases the critical delay, we accelerate the major computing path that is activated at the most of SCM lifetime, preserving the critical delay of the proposed KES module as similar to that of the original one. When the minor cases are detected, the recovery processing is added at the end of the corresponding iteration. In order to reduce the additional energy consumption due to the unfolded architecture, we carefully deactivate the internal modules during the accelerated processing, which only necessitate for the recovery cycle. Implementation results show that the proposed KES architecture greatly reduces the decoding latency of arbitrary BCH decoder, leading to the high-speed and reliable emerging storages.
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ISSN:1549-8328
1558-0806
DOI:10.1109/TCSI.2020.2976806