Low-Power Scalable TSPI: A Modular Off-Chip Network for Edge AI Accelerators

In this paper, we present a novel off-chip network architecture, the Tile Serial Peripheral Interface (TSPI), designed for low-power, scalable edge AI accelerators. Our approach modifies the conventional SPI to support a modular network structure that facilitates the scalable connection of multiple...

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Veröffentlicht in:	IEEE access Jg. 12; S. 141448 - 141459
Hauptverfasser:	Park, Seunghyun, Park, Daejin
Format:	Journal Article
Sprache:	Englisch
Veröffentlicht:	Piscataway IEEE 2024 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Schlagworte:	Accelerator architectures Accelerators Algorithms Computational modeling Computer architecture Distributed databases Edge AI Edge computing edge device Indexes low power Low power electronics Message passing Modular structures MPI Network architecture off-chip network Performance evaluation Power consumption Random access memory Scalability subset mapping algorithm TSPI
ISSN:	2169-3536, 2169-3536
Online-Zugang:	Volltext
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