Gillespie’s Stochastic Simulation Algorithm on MIC coprocessors
To investigate the behavior of biochemical systems, many runs of Gillespie’s Stochastic Simulation Algorithm (SSA) are generally needed, causing excessive computational costs on Central Processing Units (CPUs). Since all SSA runs are independent, the Intel Xeon Phi coprocessors based on the Many Int...
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| Published in: | The Journal of supercomputing Vol. 73; no. 2; pp. 676 - 686 |
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| Main Authors: | , , , , |
| Format: | Journal Article |
| Language: | English |
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01.02.2017
Springer Nature B.V |
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| ISSN: | 0920-8542, 1573-0484 |
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| Abstract | To investigate the behavior of biochemical systems, many runs of Gillespie’s Stochastic Simulation Algorithm (SSA) are generally needed, causing excessive computational costs on Central Processing Units (CPUs). Since all SSA runs are independent, the Intel Xeon Phi coprocessors based on the Many Integrated Core (MIC) architecture can be exploited to distribute the workload. We considered two execution modalities on MIC: one consisted in running exactly the same CPU code of SSA, while the other exploited MIC’s vector instructions to reuse the CPU code with only few modifications. MIC performance was compared with Graphics Processing Units (GPUs), specifically implemented in CUDA to optimize the use of memory hierarchy. Our results show that GPU largely outperforms MIC and CPU, but required a complete redesign of SSA. MIC allows a relevant speedup, especially when vector instructions are used, with the additional advantage of requiring minimal modifications to CPU code. |
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| AbstractList | To investigate the behavior of biochemical systems, many runs of Gillespie’s Stochastic Simulation Algorithm (SSA) are generally needed, causing excessive computational costs on Central Processing Units (CPUs). Since all SSA runs are independent, the Intel Xeon Phi coprocessors based on the Many Integrated Core (MIC) architecture can be exploited to distribute the workload. We considered two execution modalities on MIC: one consisted in running exactly the same CPU code of SSA, while the other exploited MIC’s vector instructions to reuse the CPU code with only few modifications. MIC performance was compared with Graphics Processing Units (GPUs), specifically implemented in CUDA to optimize the use of memory hierarchy. Our results show that GPU largely outperforms MIC and CPU, but required a complete redesign of SSA. MIC allows a relevant speedup, especially when vector instructions are used, with the additional advantage of requiring minimal modifications to CPU code. |
| Author | Cazzaniga, Paolo Besozzi, Daniela Nobile, Marco S. Mauri, Giancarlo Tangherloni, Andrea |
| Author_xml | – sequence: 1 givenname: Andrea surname: Tangherloni fullname: Tangherloni, Andrea email: tangherloni@disco.unimib.it organization: Department of Informatics, Systems and Communication, University of Milano-Bicocca – sequence: 2 givenname: Marco S. surname: Nobile fullname: Nobile, Marco S. organization: Department of Informatics, Systems and Communication, University of Milano-Bicocca, SYSBIO.IT Centre of Systems Biology – sequence: 3 givenname: Paolo surname: Cazzaniga fullname: Cazzaniga, Paolo organization: Department of Human and Social Sciences, University of Bergamo, SYSBIO.IT Centre of Systems Biology – sequence: 4 givenname: Daniela surname: Besozzi fullname: Besozzi, Daniela organization: Department of Informatics, Systems and Communication, University of Milano-Bicocca, SYSBIO.IT Centre of Systems Biology – sequence: 5 givenname: Giancarlo surname: Mauri fullname: Mauri, Giancarlo organization: Department of Informatics, Systems and Communication, University of Milano-Bicocca, SYSBIO.IT Centre of Systems Biology |
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| Cites_doi | 10.1016/j.cpc.2014.05.026 10.1007/s11227-014-1208-8 10.1016/0378-4371(92)90283-V 10.1287/opre.50.6.1073.358 10.1038/ncb1497 10.1109/MM.2010.41 10.1021/j100540a008 10.1016/j.cpc.2014.12.013 10.1186/1687-4153-2012-10 10.1007/978-3-319-21909-7_36 10.1145/2568088.2576799 10.1088/1748-0221/9/04/P04005 10.1109/IEMBS.2008.4649413 10.1109/HPCASIA.2005.67 10.1038/nrg2509 10.1109/CEC.2013.6557752 10.1007/978-3-642-29066-4_7 10.1186/1752-0509-9-S1-S6 10.1109/SBAC-PAD.2013.37 10.1007/978-3-642-39958-9_32 10.1186/1752-0509-6-91 10.1371/journal.pone.0091963 |
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| Title | Gillespie’s Stochastic Simulation Algorithm on MIC coprocessors |
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