Length-Matching-Constrained Region Routing in Rapid Single-Flux-Quantum Circuits

It is known that the pipelined architecture in a rapid single-flux-quantum (RSFQ) circuit can be constructed by inserting a set of path-balancing <inline-formula> <tex-math notation="LaTeX">D </tex-math></inline-formula>-type flip-flops (DFFs) into some gate columns...

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Vydané v:	IEEE transactions on computer-aided design of integrated circuits and systems Ročník 40; číslo 5; s. 945 - 956
Hlavný autor:	Yan, Jin-Tai
Médium:	Journal Article
Jazyk:	English
Vydavateľské údaje:	New York IEEE 01.05.2021 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Predmet:	Algorithms Area Clocks Computer architecture Constraints Extension length Gates (circuits) Insertion Iterative methods Layout length-matching constraint Logic gates Matching Partitioning algorithms rapid single-flux-quantum (RSFQ) circuit region routing Routing Timing Tracks (paths) Transmission lines
ISSN:	0278-0070, 1937-4151
On-line prístup:	Získať plný text
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