Length-Matching-Constrained Region Routing in Rapid Single-Flux-Quantum Circuits

It is known that the pipelined architecture in a rapid single-flux-quantum (RSFQ) circuit can be constructed by inserting a set of path-balancing <inline-formula> <tex-math notation="LaTeX">D </tex-math></inline-formula>-type flip-flops (DFFs) into some gate columns...

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Bibliographic Details
Published in:	IEEE transactions on computer-aided design of integrated circuits and systems Vol. 40; no. 5; pp. 945 - 956
Main Author:	Yan, Jin-Tai
Format:	Journal Article
Language:	English
Published:	New York IEEE 01.05.2021 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:	Algorithms Area Clocks Computer architecture Constraints Extension length Gates (circuits) Insertion Iterative methods Layout length-matching constraint Logic gates Matching Partitioning algorithms rapid single-flux-quantum (RSFQ) circuit region routing Routing Timing Tracks (paths) Transmission lines
ISSN:	0278-0070, 1937-4151
Online Access:	Get full text
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