Length-Matching-Constrained Region Routing in Rapid Single-Flux-Quantum Circuits
It is known that the pipelined architecture in a rapid single-flux-quantum (RSFQ) circuit can be constructed by inserting a set of path-balancing <inline-formula> <tex-math notation="LaTeX">D </tex-math></inline-formula>-type flip-flops (DFFs) into some gate columns...
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| Vydáno v: | IEEE transactions on computer-aided design of integrated circuits and systems Ročník 40; číslo 5; s. 945 - 956 |
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| Médium: | Journal Article |
| Jazyk: | angličtina |
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New York
IEEE
01.05.2021
The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
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| ISSN: | 0278-0070, 1937-4151 |
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| Abstract | It is known that the pipelined architecture in a rapid single-flux-quantum (RSFQ) circuit can be constructed by inserting a set of path-balancing <inline-formula> <tex-math notation="LaTeX">D </tex-math></inline-formula>-type flip-flops (DFFs) into some gate columns. Based on the assignment of the gates involving the splitters (SPLs) inside each gate column in the placement stage, the passive transmission line (PTL) region between two adjacent gate columns can be formed for a set of 2-pin connections in the routing stage. In this article, given a set of 2-pin connections with length-matching constraints inside one PTL region, based on the efficient utilization of available space in two routing layers, a new grid-based Manhattan routing model can be defined to use available space inside two routing layers for the insertion of the extension lengths on the given connections. To minimize the routing width inside one PTL region, a two-way track-assignment-based routing algorithm using the defined routing model can be first proposed to assign two partitioned sets of vertical intervals onto the used tracks inside two routing layers and connect the corresponding horizontal segments for the given connections with no extension length. Based on the definition of the available areas in the initial two-layer routing result, an iterative flow-based insertion algorithm can be further proposed to insert the feasible detouring paths onto the available areas for the extension lengths on the given connections. If there is no available area for the extension lengths on the unsatisfied connections, an efficient insertion algorithm can be proposed to insert the detouring paths onto one extra area for the extension lengths on the unsatisfied connections. Compared with Kito's routing algorithm and Cheng's routing algorithm in length-matching-constrained region routing, the experimental results show that our proposed routing algorithm can use reasonable CPU time to decrease 22.2% and 16.3% of the region width for 12 tested examples on the average, respectively. |
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| AbstractList | It is known that the pipelined architecture in a rapid single-flux-quantum (RSFQ) circuit can be constructed by inserting a set of path-balancing <inline-formula> <tex-math notation="LaTeX">D </tex-math></inline-formula>-type flip-flops (DFFs) into some gate columns. Based on the assignment of the gates involving the splitters (SPLs) inside each gate column in the placement stage, the passive transmission line (PTL) region between two adjacent gate columns can be formed for a set of 2-pin connections in the routing stage. In this article, given a set of 2-pin connections with length-matching constraints inside one PTL region, based on the efficient utilization of available space in two routing layers, a new grid-based Manhattan routing model can be defined to use available space inside two routing layers for the insertion of the extension lengths on the given connections. To minimize the routing width inside one PTL region, a two-way track-assignment-based routing algorithm using the defined routing model can be first proposed to assign two partitioned sets of vertical intervals onto the used tracks inside two routing layers and connect the corresponding horizontal segments for the given connections with no extension length. Based on the definition of the available areas in the initial two-layer routing result, an iterative flow-based insertion algorithm can be further proposed to insert the feasible detouring paths onto the available areas for the extension lengths on the given connections. If there is no available area for the extension lengths on the unsatisfied connections, an efficient insertion algorithm can be proposed to insert the detouring paths onto one extra area for the extension lengths on the unsatisfied connections. Compared with Kito's routing algorithm and Cheng's routing algorithm in length-matching-constrained region routing, the experimental results show that our proposed routing algorithm can use reasonable CPU time to decrease 22.2% and 16.3% of the region width for 12 tested examples on the average, respectively. It is known that the pipelined architecture in a rapid single-flux-quantum (RSFQ) circuit can be constructed by inserting a set of path-balancing [Formula Omitted]-type flip-flops (DFFs) into some gate columns. Based on the assignment of the gates involving the splitters (SPLs) inside each gate column in the placement stage, the passive transmission line (PTL) region between two adjacent gate columns can be formed for a set of 2-pin connections in the routing stage. In this article, given a set of 2-pin connections with length-matching constraints inside one PTL region, based on the efficient utilization of available space in two routing layers, a new grid-based Manhattan routing model can be defined to use available space inside two routing layers for the insertion of the extension lengths on the given connections. To minimize the routing width inside one PTL region, a two-way track-assignment-based routing algorithm using the defined routing model can be first proposed to assign two partitioned sets of vertical intervals onto the used tracks inside two routing layers and connect the corresponding horizontal segments for the given connections with no extension length. Based on the definition of the available areas in the initial two-layer routing result, an iterative flow-based insertion algorithm can be further proposed to insert the feasible detouring paths onto the available areas for the extension lengths on the given connections. If there is no available area for the extension lengths on the unsatisfied connections, an efficient insertion algorithm can be proposed to insert the detouring paths onto one extra area for the extension lengths on the unsatisfied connections. Compared with Kito’s routing algorithm and Cheng’s routing algorithm in length-matching-constrained region routing, the experimental results show that our proposed routing algorithm can use reasonable CPU time to decrease 22.2% and 16.3% of the region width for 12 tested examples on the average, respectively. |
| Author | Yan, Jin-Tai |
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| Cites_doi | 10.1088/0953-2048/26/1/015002 10.1109/TASC.2016.2642049 10.1145/800158.805069 10.1109/TASC.2010.2098432 10.1016/j.physc.2012.03.031 10.1109/TASC.2018.2793203 10.1109/TASC.2010.2096792 10.1109/77.80745 10.1093/ietfec/e91-a.12.3772 10.1145/3240765.3243487 10.1093/ietele/E88-C.2.198 10.1109/TASC.2015.2399866 10.1109/77.783712 10.1109/TASC.2014.2378593 10.1109/TASC.2013.2240555 10.1109/TASC.2019.2955095 |
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| Snippet | It is known that the pipelined architecture in a rapid single-flux-quantum (RSFQ) circuit can be constructed by inserting a set of path-balancing... It is known that the pipelined architecture in a rapid single-flux-quantum (RSFQ) circuit can be constructed by inserting a set of path-balancing [Formula... |
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| SubjectTerms | Algorithms Area Clocks Computer architecture Constraints Extension length Gates (circuits) Insertion Iterative methods Layout length-matching constraint Logic gates Matching Partitioning algorithms rapid single-flux-quantum (RSFQ) circuit region routing Routing Timing Tracks (paths) Transmission lines |
| Title | Length-Matching-Constrained Region Routing in Rapid Single-Flux-Quantum Circuits |
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