3D EM/MPM Image Segmentation Using an FPGA Embedded Design Implementation

This paper presents a Field Programmable Gate Array (FPGA) based embedded system which is used to achieve high speed segmentation of 3D images. Segmentation is performed using Expectation-Maximization (EM) with Maximization of Posterior Marginals (MPM) Bayesian algorithm. This algorithm segments the...

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Vydáno v:Journal of signal processing systems Ročník 81; číslo 3; s. 411 - 424
Hlavní autoři: Liu, Chao, Sun, Yan, Christopher, Lauren
Médium: Journal Article
Jazyk:angličtina
Vydáno: New York Springer US 01.12.2015
Témata:
Circuits and Systems
Computer Imaging
Electrical Engineering
Engineering
Image Processing and Computer Vision
Pattern Recognition
Pattern Recognition and Graphics
Signal,Image and Speech Processing
Vision
FPGA
3D image segmentation
EM/MPM
ISSN:1939-8018, 1939-8115
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Popis
Shrnutí:This paper presents a Field Programmable Gate Array (FPGA) based embedded system which is used to achieve high speed segmentation of 3D images. Segmentation is performed using Expectation-Maximization (EM) with Maximization of Posterior Marginals (MPM) Bayesian algorithm. This algorithm segments the 3D image using neighboring pixels based on a Markov Random Field (MRF) model. In this system, the embedded processor controls a custom circuit which performs the MPM and portions of the EM algorithm. The embedded processor completes the EM algorithm and also controls image data transmission between host computer and on-board memory. The whole system has been implemented on Xilinx Virtex 6 FPGA and achieved over 100 times processing improvement compared to standard desktop computer. Three new techniques were the key to achieve this speed: Pipelined computational cores, sixteen parallel data paths and a novel memory interface for maximizing the external memory bandwidth.
ISSN:1939-8018
1939-8115
DOI:10.1007/s11265-014-0965-1