High-Throughput Soft-Output MIMO Detector Based on Path-Preserving Trellis-Search Algorithm
In this paper, we propose a novel path-preserving trellis-search (PPTS) algorithm and its high-speed VLSI architecture for soft-output multiple-input-multiple-output (MIMO) detection. We represent the search space of the MIMO signal with an unconstrained trellis, where each node in stage k of the tr...
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| Vydáno v: | IEEE transactions on very large scale integration (VLSI) systems Ročník 20; číslo 7; s. 1235 - 1247 |
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| Médium: | Journal Article |
| Jazyk: | angličtina |
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New York, NY
IEEE
01.07.2012
Institute of Electrical and Electronics Engineers The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
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| ISSN: | 1063-8210, 1557-9999 |
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| Abstract | In this paper, we propose a novel path-preserving trellis-search (PPTS) algorithm and its high-speed VLSI architecture for soft-output multiple-input-multiple-output (MIMO) detection. We represent the search space of the MIMO signal with an unconstrained trellis, where each node in stage k of the trellis maps to a possible complex-valued symbol transmitted by antenna k . Based on the trellis model, we convert the soft-output MIMO detection problem into a multiple shortest paths problem subject to the constraint that every trellis node must be covered in this set of paths. The PPTS detector is guaranteed to have soft information for every possible symbol transmitted on every antenna so that the log-likelihood ratio (LLR) for each transmitted data bit can be more accurately formed. Simulation results show that the PPTS algorithm can achieve near-optimal error performance with a low search complexity. The PPTS algorithm is a hardware-friendly data-parallel algorithm because the search operations are evenly distributed among multiple trellis nodes for parallel processing. As a case study, we have designed and synthesized a fully-parallel systolic-array detector and two folded detectors for a 4 × 4 16-QAM system using a 1.08 V TSMC 65-nm CMOS technology. With a 1.18 mm 2 core area, the folded detector can achieve a throughput of 2.1 Gbps. With a 3.19 mm 2 core area, the fully-parallel systolic-array detector can achieve a throughput of 6.4 Gbps. |
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| AbstractList | In this paper, we propose a novel path-preserving trellis-search (PPTS) algorithm and its high-speed VLSI architecture for soft-output multiple-input-multiple-output (MIMO) detection. We represent the search space of the MIMO signal with an unconstrained trellis, where each node in stage k of the trellis maps to a possible complex-valued symbol transmitted by antenna k . Based on the trellis model, we convert the soft-output MIMO detection problem into a multiple shortest paths problem subject to the constraint that every trellis node must be covered in this set of paths. The PPTS detector is guaranteed to have soft information for every possible symbol transmitted on every antenna so that the log-likelihood ratio (LLR) for each transmitted data bit can be more accurately formed. Simulation results show that the PPTS algorithm can achieve near-optimal error performance with a low search complexity. The PPTS algorithm is a hardware-friendly data-parallel algorithm because the search operations are evenly distributed among multiple trellis nodes for parallel processing. As a case study, we have designed and synthesized a fully-parallel systolic-array detector and two folded detectors for a 4 × 4 16-QAM system using a 1.08 V TSMC 65-nm CMOS technology. With a 1.18 mm 2 core area, the folded detector can achieve a throughput of 2.1 Gbps. With a 3.19 mm 2 core area, the fully-parallel systolic-array detector can achieve a throughput of 6.4 Gbps. In this paper, we propose a novel path-preserving trellis-search (PPTS) algorithm and its high-speed VLSI architecture for soft-output multiple-input-multiple-output (MIMO) detection. We represent the search space of the MIMO signal with an unconstrained trellis, where each node in stage [Formula Omitted] of the trellis maps to a possible complex-valued symbol transmitted by antenna [Formula Omitted]. Based on the trellis model, we convert the soft-output MIMO detection problem into a multiple shortest paths problem subject to the constraint that every trellis node must be covered in this set of paths. The PPTS detector is guaranteed to have soft information for every possible symbol transmitted on every antenna so that the log-likelihood ratio (LLR) for each transmitted data bit can be more accurately formed. Simulation results show that the PPTS algorithm can achieve near-optimal error performance with a low search complexity. The PPTS algorithm is a hardware-friendly data-parallel algorithm because the search operations are evenly distributed among multiple trellis nodes for parallel processing. As a case study, we have designed and synthesized a fully-parallel systolic-array detector and two folded detectors for a 4 [Formula Omitted] 4 16-QAM system using a 1.08 V TSMC 65-nm CMOS technology. With a 1.18 mm[Formula Omitted] core area, the folded detector can achieve a throughput of 2.1 Gbps. With a 3.19 mm[Formula Omitted] core area, the fully-parallel systolic-array detector can achieve a throughput of 6.4 Gbps. In this paper, we propose a novel path-preserving trellis-search (PPTS) algorithm and its high-speed VLSI architecture for soft-output multiple-input-multiple-output (MIMO) detection. We represent the search space of the MIMO signal with an unconstrained trellis, where each node in stage k of the trellis maps to a possible complex-valued symbol transmitted by antenna k . Based on the trellis model, we convert the soft-output MIMO detection problem into a multiple shortest paths problem subject to the constraint that every trellis node must be covered in this set of paths. The PPTS detector is guaranteed to have soft information for every possible symbol transmitted on every antenna so that the log-likelihood ratio (LLR) for each transmitted data bit can be more accurately formed. Simulation results show that the PPTS algorithm can achieve near-optimal error performance with a low search complexity. The PPTS algorithm is a hardware-friendly data-parallel algorithm because the search operations are evenly distributed among multiple trellis nodes for parallel processing. As a case study, we have designed and synthesized a fully-parallel systolic-array detector and two folded detectors for a 4 4 16-QAM system using a 1.08 V TSMC 65-nm CMOS technology. With a 1.18 mm 2 core area, the folded detector can achieve a throughput of 2.1 Gbps. With a 3.19 mm 2 core area, the fully-parallel systolic-array detector can achieve a throughput of 6.4 Gbps. |
| Author | Cavallaro, Joseph R. Yang Sun |
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| Keywords | MIMO system shortest path algorithm Parallel algorithm multiple-input-multiple-output (MIMO) detection VLSI circuit Quadrature amplitude modulation Error estimation Measurement sensor Shortest path Data transmission VLSI architecture Systolic network Application-specific integrated circuit (ASIC) Search algorithm Circuit architecture Case study Complementary MOS technology Integrated circuit Parallel processing Custom circuit soft-output MIMO detector |
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| SubjectTerms | Algorithms Antennas Application-specific integrated circuit (ASIC) Applied sciences Complexity theory Computer simulation Design. Technologies. Operation analysis. Testing Detection algorithms Detectors Electronics Exact sciences and technology General equipment and techniques Instruments, apparatus, components and techniques common to several branches of physics and astronomy Integrated circuits MIMO multiple-input-multiple-output (MIMO) detection Physics Searching Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Sensors (chemical, optical, electrical, movement, gas, etc.); remote sensing shortest path algorithm soft-output MIMO detector Studies Symbols Throughput Transmitting antennas Very large scale integration VLSI architecture |
| Title | High-Throughput Soft-Output MIMO Detector Based on Path-Preserving Trellis-Search Algorithm |
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