Real-Time Computation of Local Neighborhood Functions in Application-Specific Instruction-Set Processors
This paper presents a systematic approach to the design of application-specific instruction-set processors for high speed computation of local neighborhood functions and intra-field deinterlacing. The intended application is real-time processing of high definition video. The approach aims at an effi...
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| Vydané v: | IEEE transactions on very large scale integration (VLSI) systems Ročník 20; číslo 11; s. 2031 - 2043 |
|---|---|
| Hlavní autori: | , , |
| Médium: | Journal Article |
| Jazyk: | English |
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New York, NY
IEEE
01.11.2012
Institute of Electrical and Electronics Engineers The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
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| ISSN: | 1063-8210, 1557-9999 |
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| Abstract | This paper presents a systematic approach to the design of application-specific instruction-set processors for high speed computation of local neighborhood functions and intra-field deinterlacing. The intended application is real-time processing of high definition video. The approach aims at an efficient utilization of the available memory bandwidth by fully exploiting the data parallelism inherent to the target algorithm class. An appropriate choice of custom instructions and application-specific registers is used together with a very long instruction word architecture in order to mimic a pipelined systolic array. This leads to a processing speed close to the limit imposed by memory bandwidth constraints. For three intra-field deinterlacing algorithms and 2-D convolution with four kernel sizes, the design approach yields speedup factors between 36 and 1330, Area-Time (AT) product improvements between 12× and 243×, and energy consumption reduction factors between 13 and 262. |
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| AbstractList | This paper presents a systematic approach to the design of application-specific instruction-set processors for high speed computation of local neighborhood functions and intra-field deinterlacing. The intended application is real-time processing of high definition video. The approach aims at an efficient utilization of the available memory bandwidth by fully exploiting the data parallelism inherent to the target algorithm class. An appropriate choice of custom instructions and application-specific registers is used together with a very long instruction word architecture in order to mimic a pipelined systolic array. This leads to a processing speed close to the limit imposed by memory bandwidth constraints. For three intra-field deinterlacing algorithms and 2-D convolution with four kernel sizes, the design approach yields speedup factors between 36 and 1330, Area-Time (AT) product improvements between 12× and 243×, and energy consumption reduction factors between 13 and 262. This paper presents a systematic approach to the design of application-specific instruction-set processors for high speed computation of local neighborhood functions and intra-field deinterlacing. The intended application is real-time processing of high definition video. The approach aims at an efficient utilization of the available memory bandwidth by fully exploiting the data parallelism inherent to the target algorithm class. An appropriate choice of custom instructions and application-specific registers is used together with a very long instruction word architecture in order to mimic a pipelined systolic array. This leads to a processing speed close to the limit imposed by memory bandwidth constraints. For three intra-field deinterlacing algorithms and 2-D convolution with four kernel sizes, the design approach yields speedup factors between 36 and 1330, Area-Time (AT) product improvements between 12 and 243 , and energy consumption reduction factors between 13 and 262. This paper presents a systematic approach to the design of application-specific instruction-set processors for high speed computation of local neighborhood functions and intra-field deinterlacing. The intended application is real-time processing of high definition video. The approach aims at an efficient utilization of the available memory bandwidth by fully exploiting the data parallelism inherent to the target algorithm class. An appropriate choice of custom instructions and application-specific registers is used together with a very long instruction word architecture in order to mimic a pipelined systolic array. This leads to a processing speed close to the limit imposed by memory bandwidth constraints. For three intra-field deinterlacing algorithms and 2-D convolution with four kernel sizes, the design approach yields speedup factors between 36 and 1330, Area-Time (AT) product improvements between 12[Formula Omitted] and 243[Formula Omitted], and energy consumption reduction factors between 13 and 262. |
| Author | Aubertin, P. Langlois, J. M. P. Savaria, Y. |
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| Keywords | Application-specific instruction-set processors (ASIPs) High resolution Processor Instruction sets local neighborhood functions Systolic network Algorithm Video signal processing video processing Kernel method Very long instruction word Pipeline network Integrated circuit Electric power consumption Parallelism Millimeter wave integrated circuits Real time processing Monolithic integrated circuit Resource management Custom circuit deinterlacing |
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| SubjectTerms | Algorithms Application specific processors Application-specific instruction-set processors (ASIPs) Applied sciences Circuit properties Computation Computer architecture deinterlacing Design engineering Design. Technologies. Operation analysis. Testing Electric, optical and optoelectronic circuits Electronics Exact sciences and technology High definition video Image edge detection Integrated circuits Integrated circuits by function (including memories and processors) local neighborhood functions Mathematical analysis Mathematical models Microwave circuits, microwave integrated circuits, microwave transmission lines, submillimeter wave circuits Processors Program processors Real time Real time systems Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Studies Very large scale integration video processing |
| Title | Real-Time Computation of Local Neighborhood Functions in Application-Specific Instruction-Set Processors |
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