Scalable Packet Classification on FPGA

Multi-field packet classification has evolved from traditional fixed 5-tuple matching to flexible matching with arbitrary combination of numerous packet header fields. For example, the recently proposed OpenFlow switching requires classifying each packet using up to 12-tuple packet header fields. It...

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Veröffentlicht in:	IEEE transactions on very large scale integration (VLSI) systems Jg. 20; H. 9; S. 1668 - 1680
Hauptverfasser:	Weirong Jiang, Prasanna, V. K.
Format:	Journal Article
Sprache:	Englisch
Veröffentlicht:	New York, NY IEEE 01.09.2012 Institute of Electrical and Electronics Engineers The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Schlagworte:	Algorithm design and analysis Applied sciences Architecture Circuit properties Classification Decision tree Decision trees Design. Technologies. Operation analysis. Testing Digital circuits Electric, optical and optoelectronic circuits Electronic circuits Electronics Exact sciences and technology Field programmable gate arrays field-programmable gate array (FPGA) Headers Integrated circuits Integrated circuits by function (including memories and processors) Matching Next generation networking openflow packet classification Partitioning algorithms pipeline Pipeline processing Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices SRAM State of the art Studies Sustaining Throughput Very large scale integration Static random access memory State of the art Scalability Random access memory Mapping Field programmable gate array openflow Algorithm Decision tree SRAM field-programmable gate array (FPGA) Switching Implementation Optimization pipeline packet classification Non volatile memory Storage management Integrated circuit Parallelism
ISSN:	1063-8210, 1557-9999
Online-Zugang:	Volltext
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