Scalable Packet Classification on FPGA

Multi-field packet classification has evolved from traditional fixed 5-tuple matching to flexible matching with arbitrary combination of numerous packet header fields. For example, the recently proposed OpenFlow switching requires classifying each packet using up to 12-tuple packet header fields. It...

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Vydané v:IEEE transactions on very large scale integration (VLSI) systems Ročník 20; číslo 9; s. 1668 - 1680
Hlavní autori: Weirong Jiang, Prasanna, V. K.
Médium: Journal Article
Jazyk:English
Vydavateľské údaje: New York, NY IEEE 01.09.2012
Institute of Electrical and Electronics Engineers
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Predmet:
Algorithm design and analysis
Applied sciences
Architecture
Circuit properties
Classification
Decision tree
Decision trees
Design. Technologies. Operation analysis. Testing
Digital circuits
Electric, optical and optoelectronic circuits
Electronic circuits
Electronics
Exact sciences and technology
Field programmable gate arrays
field-programmable gate array (FPGA)
Headers
Integrated circuits
Integrated circuits by function (including memories and processors)
Matching
Next generation networking
openflow
packet classification
Partitioning algorithms
pipeline
Pipeline processing
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
SRAM
State of the art
Studies
Sustaining
Throughput
Very large scale integration
Static random access memory
State of the art
Scalability
Random access memory
Mapping
Field programmable gate array
openflow
Algorithm
Decision tree
SRAM
field-programmable gate array (FPGA)
Switching
Implementation
Optimization
pipeline
packet classification
Non volatile memory
Storage management
Integrated circuit
Parallelism
ISSN:1063-8210, 1557-9999
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Popis
Shrnutí:Multi-field packet classification has evolved from traditional fixed 5-tuple matching to flexible matching with arbitrary combination of numerous packet header fields. For example, the recently proposed OpenFlow switching requires classifying each packet using up to 12-tuple packet header fields. It has become a great challenge to develop scalable solutions for next-generation packet classification that support higher throughput, larger rule sets and more packet header fields. This paper exploits the abundant parallelism and other desirable features provided by current field-programmable gate arrays (FPGAs), and proposes a decision-tree-based, 2-D multi-pipeline architecture for next-generation packet classification. We revisit the techniques for traditional 5-tuple packet classification and propose several optimization techniques for the state-of-the-art decision-tree-based algorithm. Given a set of 12-tuple rules, we develop a framework to partition the rule set into multiple subsets each of which is built into an optimized decision tree. A tree-to-pipeline mapping scheme is carefully designed to maximize the memory utilization while sustaining high throughput. The implementation results show that our architecture can store either 10K real-life 5-tuple rules or 1K synthetic 12-tuple rules in on-chip memory of a single state-of-the-art FPGA, and sustain 80 and 40 Gbps throughput for minimum size (40 bytes) packets, respectively.
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ISSN:1063-8210
1557-9999
DOI:10.1109/TVLSI.2011.2162112