Improving Multi-Level NAND Flash Memory Storage Reliability Using Concatenated BCH-TCM Coding

By storing more than one bit in each memory cell, multi-level per cell (MLC) NAND flash memories are dominating global flash memory market due to their appealing storage density advantage. However, continuous technology scaling makes MLC NAND flash memories increasingly subject to worse raw storage...

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Bibliographic Details
Published in:IEEE transactions on very large scale integration (VLSI) systems Vol. 18; no. 10; pp. 1412 - 1420
Main Authors: Li, Shu, Zhang, Tong
Format: Journal Article
Language:English
Published: New York, NY IEEE 01.10.2010
Institute of Electrical and Electronics Engineers
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:
Applied sciences
BCH codes
Bit error rate
Circuit properties
Coding
Computer simulation
Concatenated codes
Costs
Demodulation
Density
Design engineering
Design. Technologies. Operation analysis. Testing
Digital circuits
Electric, optical and optoelectronic circuits
Electronic circuits
Electronics
Error correction codes
Error rate
Exact sciences and technology
Fault tolerance
Flash memory
Flash memory (computers)
hardware cost
Integrated circuits
Integrated circuits by function (including memories and processors)
Magnetic and optical mass memories
Markets
Memory
Modulation coding
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Semiconductors
Silicon
Storage and reproduction of information
Studies
throughput
trellis-coded modulation (TCM)
Very large scale integration
Performance evaluation
hardware cost
Memory devices
Bit error rate
Error rate
trellis-coded modulation (TCM)
Static storage
Implementation
Logic circuit
Fault tolerance
Non volatile memory
Coding
Recording density
Trellis coded modulation
Silicon
throughput
Multilevel system
NAND circuit
Computer simulation
Flash memory
Integrated circuit
Error correction
Miniaturization
Reliability
Custom circuit
Demodulation
ISSN:1063-8210, 1557-9999
Online Access:Get full text
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Description
Summary:By storing more than one bit in each memory cell, multi-level per cell (MLC) NAND flash memories are dominating global flash memory market due to their appealing storage density advantage. However, continuous technology scaling makes MLC NAND flash memories increasingly subject to worse raw storage reliability. This paper presents a memory fault tolerance design solution geared to MLC NAND flash memories. The basic idea is to concatenate trellis coded modulation (TCM) with an outer BCH code, which can greatly improve the error correction performance compared with the current design practice that uses BCH codes only. The key is that TCM can well leverage the multi-level storage characteristic to reduce the memory bit error rate and hence relieve the burden of outer BCH code, at no cost of extra redundant memory cells. The superior performance of such concatenated BCH-TCM coding systems for MLC NAND flash memories has been well demonstrated through computer simulations. A modified TCM demodulation approach is further proposed to improve the tolerance to static memory cell defects. We also address the associated practical implementation issues in case of using either single-page or multi-page programming strategy, and demonstrate the silicon implementation efficiency through application-specific integrated circuit design at 65 nm node.
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ISSN:1063-8210
1557-9999
DOI:10.1109/TVLSI.2009.2024154