A Compact Model for ISPP of 3-D Charge-Trap NAND Flash Memories

We developed a compact model for program transient simulation of 3-D charge-trap NAND flash on a bitline (BL) string level. By implanting the trapped charge parameters and the solutions obtained from modified 1-D Poisson equation into our unit cell model, we suggest that our model shows better accur...

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Veröffentlicht in:IEEE transactions on electron devices Jg. 67; H. 8; S. 3095 - 3101
Hauptverfasser: Kim, Minsoo, Kim, Sungbak, Shin, Hyungcheol
Format: Journal Article
Sprache:Englisch
Veröffentlicht: New York IEEE 01.08.2020
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Schlagworte:
3-D charge-trap NAND flash memories
compact model
Computer simulation
Data models
Electron traps
Electron tunneling
incremental step pulse programming (ISPP)
Integrated circuit modeling
Logic gates
Mathematical model
Mathematical models
Model accuracy
Parameter modification
Poisson equation
program transient operation
simulation program with integrated circuit emphasis (SPICE)
Solid modeling
Three dimensional models
Transient analysis
Trapped charge
Unit cell
ISSN:0018-9383, 1557-9646
Online-Zugang:Volltext
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Zusammenfassung:We developed a compact model for program transient simulation of 3-D charge-trap NAND flash on a bitline (BL) string level. By implanting the trapped charge parameters and the solutions obtained from modified 1-D Poisson equation into our unit cell model, we suggest that our model shows better accuracy compared to the existing model. After fitting the measured incremental step pulse programming (ISPP) data with the best accuracy, we investigated our model dependence on parameters relevant to electron tunneling/capture/emission and channel scaling. Also, the simulation results from various pulse conditions are investigated. Finally, program-inhibit characteristics by isolated channel were simulated and analyzed. Thus, we propose a widely available, highly accurate, and physics-based compact model for program operation of 3-D charge-trap NAND flash memories.
Bibliographie:ObjectType-Article-1
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content type line 14
ISSN:0018-9383
1557-9646
DOI:10.1109/TED.2020.3000448