A Fully Polynomial-Time Approximation Scheme for Timing-Constrained Minimum Cost Layer Assignment

As VLSI technology enters the nanoscale regime, the interconnect delay becomes the bottleneck of circuit performance. Compared with gate delays, wires are becoming increasingly resistive, making it more difficult to propagate signals across the chip. However, more advanced technologies (65 and 45 nm...

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Bibliographic Details
Published in:	IEEE transactions on circuits and systems. II, Express briefs Vol. 56; no. 7; pp. 580 - 584
Main Authors:	Hu, Shiyan, Li, Zhuo, Alpert, Charles J.
Format:	Journal Article
Language:	English
Published:	New York IEEE 01.07.2009 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:	Algorithms Approximation Circuit optimization Costs Delay Fully polynomial-time approximation scheme (FPTAS) Integrated circuit interconnections interconnect synthesis layer assignment Mathematical analysis Metals Minimum cost Nanostructure NP-complete NP-complete problem Polynomials Propagation delay Routing Studies Time measurements Timing Very large scale integration Wire Wires
ISSN:	1549-7747, 1558-3791
Online Access:	Get full text
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