A 280 mV-to-1.1 V 256b Reconfigurable SIMD Vector Permutation Engine With 2-Dimensional Shuffle in 22 nm Tri-Gate CMOS

An ultra-low voltage reconfigurable 4-way to 32-way SIMD vector permutation engine is fabricated in 22 nm tri-gate bulk CMOS, consisting of a 32-entry × 256b 3-read/1-write ported register file with a 256b byte-wise any-to-any permute crossbar for 2-dimensional shuffle. The register file integrates...

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Bibliographic Details
Published in:	IEEE journal of solid-state circuits Vol. 48; no. 1; pp. 118 - 127
Main Authors:	Hsu, S. K., Agarwal, A., Anders, M. A., Mathew, S. K., Kaul, H., Sheikh, F., Krishnamurthy, R. K.
Format:	Journal Article Conference Proceeding
Language:	English
Published:	New York, NY IEEE 01.01.2013 Institute of Electrical and Electronics Engineers The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:	Applied sciences Circuit properties crossbar Design. Technologies. Operation analysis. Testing Digital circuits Direct power generation Electric potential Electric, optical and optoelectronic circuits Electronic circuits Electronics Energy efficiency Energy measurement Engines Exact sciences and technology flip-flop Integrated circuits Integrated optics. Optical fibers and wave guides level shifter Logic gates Mathematical analysis Multiplexing near-threshold voltage (NTV) Optical and optoelectronic circuits permutation Permutations register file Registers Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Single instruction multiple data (SIMD) Switching, multiplexing, switched capacity circuits ultra-low voltage vector processing Vectors Vectors (mathematics) Voltage Voltage measurement {\rm V}_{\rm MIN} Performance evaluation Interconnection network Scalability ultra-low voltage Stacking Multiplexer Clock Implementation vector processing Semiconductor optical amplifiers Low voltage Flip-flop circuits Energetic efficiency Complementary MOS technology Output voltage Delay time Reconfigurable architectures crossbar Dynamic response Permutation Ultralow voltage Buffer system Algorithm Energy savings Register file level shifter VMIN, near-threshold voltage (NTV) Single instruction multiple data (SIMD) flip-flop
ISSN:	0018-9200, 1558-173X
Online Access:	Get full text
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