A low-area unified hardware architecture for the AES and the cryptographic hash function ECHO
We propose a compact coprocessor for the AES (encryption, decryption, and key expansion) and the cryptographic hash function ECHO on Virtex-5 and Virtex-6 FPGAs. Our architecture is built around an 8-bit datapath. The Arithmetic and Logic Unit performs a single instruction that allows for implementi...
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| Published in: | Journal of cryptographic engineering Vol. 1; no. 2; pp. 101 - 121 |
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| ISSN: | 2190-8508, 2190-8516 |
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| Abstract | We propose a compact coprocessor for the AES (encryption, decryption, and key expansion) and the cryptographic hash function ECHO on Virtex-5 and Virtex-6 FPGAs. Our architecture is built around an 8-bit datapath. The Arithmetic and Logic Unit performs a single instruction that allows for implementing AES encryption, AES decryption, AES key expansion, and ECHO at all levels of security. Thanks to a careful organization of AES and ECHO internal states in the register file, we manage to generate all read and write addresses by means of a modulo-16 counter and a modulo-256 counter. A fully autonomous implementation of ECHO and AES on a Virtex-5 FPGA requires 193 slices and a single 36k memory block, and achieves competitive throughputs. Assuming that the security guarantees of ECHO are at least as good as the ones of the SHA-3 finalists BLAKE and Keccak, our results show that ECHO is a better candidate for low-area cryptographic coprocessors. Furthermore, the design strategy described in this work can be applied to combine the AES and the SHA-3 finalist Grøstl. |
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| AbstractList | We propose a compact coprocessor for the AES (encryption, decryption, and key expansion) and the cryptographic hash function ECHO on Virtex-5 and Virtex-6 FPGAs. Our architecture is built around an 8-bit datapath. The Arithmetic and Logic Unit performs a single instruction that allows for implementing AES encryption, AES decryption, AES key expansion, and ECHO at all levels of security. Thanks to a careful organization of AES and ECHO internal states in the register file, we manage to generate all read and write addresses by means of a modulo-16 counter and a modulo-256 counter. A fully autonomous implementation of ECHO and AES on a Virtex-5 FPGA requires 193 slices and a single 36k memory block, and achieves competitive throughputs. Assuming that the security guarantees of ECHO are at least as good as the ones of the SHA-3 finalists BLAKE and Keccak, our results show that ECHO is a better candidate for low-area cryptographic coprocessors. Furthermore, the design strategy described in this work can be applied to combine the AES and the SHA-3 finalist Grøstl. |
| Author | Beuchat, Jean-Luc Okamoto, Eiji Yamazaki, Teppei |
| Author_xml | – sequence: 1 givenname: Jean-Luc surname: Beuchat fullname: Beuchat, Jean-Luc email: jeanluc.beuchat@gmail.com organization: Graduate School of Systems and Information Engineering, University of Tsukuba – sequence: 2 givenname: Eiji surname: Okamoto fullname: Okamoto, Eiji organization: Graduate School of Systems and Information Engineering, University of Tsukuba – sequence: 3 givenname: Teppei surname: Yamazaki fullname: Yamazaki, Teppei organization: Graduate School of Systems and Information Engineering, University of Tsukuba |
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| CitedBy_id | crossref_primary_10_1109_TCSI_2020_2997916 crossref_primary_10_1016_j_jpdc_2017_01_029 crossref_primary_10_1109_TC_2015_2435775 crossref_primary_10_1016_j_micpro_2013_05_005 crossref_primary_10_1109_TCSI_2013_2278385 |
| Cites_doi | 10.1007/978-3-642-10366-7_10 10.1049/cp.2010.0478 10.1109/DSD.2006.40 10.1109/ReConFig.2010.44 10.1007/978-0-387-71817-0_10 10.1007/11751632_32 10.1007/978-3-540-28632-5_26 10.1109/FPT.2010.5681776 10.1007/3-540-45682-1_30 10.1007/978-3-642-17455-1_25 10.1109/ISIAS.2010.5604066 10.1007/978-3-540-68164-9_2 10.1007/978-3-642-19574-7_7 10.1109/DSD.2009.162 10.1109/TCSI.2006.875179 10.1007/978-3-662-04722-4 10.1007/11545262_31 |
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| Keywords | Hash functions SHA-3 ECHO FPGA AES |
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| References | GajK.ChodowiecP.KocÇ.K.FPGA and ASIC implementations of the AESCryptographic Engineering2009New YorkSpringer23529410.1007/978-0-387-71817-0_10 El-Hadedy, M., Margala, M., Gligoroski, D., Knapskog, S.J.: Resource-efficient implementation of Blue Midnight Wish-256 hash function on Xilinx FPGA platform. In: The Second SHA-3 Candidate Conference, August 2010 Benadjila, R., Billet, O., Gueron, S., Robshaw, M.J.B.: The Intel AES instructions set and the SHA-3 candidates. In: Matsui, M. (ed.) Advances in Cryptology—ASIACRYPT 2009. Lecture Notes in Computer Science, vol. 5912, pp. 162–178. Springer, New York (2009) Aumasson, J.-P., Henzen, L., Meier, W., Phan, R.C.-W.: SHA-3 proposal BLAKE (version 1.3). http://www.131002.net/blake (2009) El-Hadedy, M., Gligoroski, D., Knapskog, S.J.: Single core implementation of Blue Midnight Wish hash function on VIRTEX 5 platform. http://tinyurl.com/3xhvx6c (2010) Wolkerstorfer, J.: An ASIC implementation of the AES-MixColumn operation. In: Rössler, P., Döderlein, A. (eds.) Proceedings of Austrochip 2001, pp. 129–132 (2001) Boneh, D., Lynn, B., Shacham, H.: Short signatures from the Weil pairing. In: Boyd, C. (ed.) Advances in Cryptology—ASIACRYPT 2001. Lecture Notes in Computer Science, vol. 2248, pp. 514–532. Springer, New York (2001) Hämäläinen, P., Alho, T., Hännikäinen, M., Hämäläinen, T.D.: Design and implementation of low-area and low-power AES encryption hardware core. In: Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools—DSD’06, pp. 577–583. IEEE Computer Society (2006) Baldwin, B., Byrne, A., Lu, L., Hamilton, M., Hanley, N., O’Neill, N., Marnane, W.P.: A hardware wrapper for the SHA-3 hash algorithms. Cryptology ePrint Archive, Report 2010/124 (2010) Bulens, P., Standaert, F.-X., Quisquater, J.-J., Pellegrin, P., Rouvroy, G.: Implementation of the AES-128 on Virtex-5 FPGAs. In: Vaudenay, S. (ed.) Progress in Cryptology—AFRICACRYPT 2008. Lecture Notes in Computer Science, vol. 5023, pp. 16–26. Springer, New York (2008) Good, T., Benaissa, M.: AES on FPGA from the fastest to the smallest. In: Rao, J.R., Sunar, B. (eds.) Cryptographic Hardware and Embedded Systems—CHES 2005. Lecture Notes in Computer Science, vol. 3659, pp. 427–440. Springer, New York (2005) Feldhofer, M., Dominikus, S., Wolkerstorfer, J.: Strong authentication for RFID systems using the AES algorithm. In: Joye, M., Quisquater, J.-J. (eds.) Cryptographic Hardware and Embedded Systems—CHES 2004. Lecture Notes in Computer Science, vol. 3156, pp. 357–370. Springer, New York (2004) Benadjila, R., Billet, O., Gilbert, H., Macario-Rat, G., Peyrin, T., Robshaw, M., Seurin, Y.: SHA-3 proposal: ECHO. http://crypto.rd.francetelecom.com/echo (2009) Järvinen, K.: Sharing resources between AES and the SHA-3 second round candidates Fugue and Grøstl. In: The Second SHA-3 Candidate Conference (2010) Aranha, D.F., Beuchat, J.-L., Detrey, J., Estibals, N.: Optimal Eta pairing on supersingular genus-2 binary hyperelliptic curves. Cryptology ePrint Archive, Report 2010/559 (2010) Feron, R., Francq, J.: FPGA implementation of Shabal: Our first results. http://www.shabal.com (2010) DaemenJ.RijmenV.The Design of Rijndael2002New YorkSpringer1065.94005 Detrey, J., Gaudry, P., Khalfallah, K.: A low-area yet performant FPGA implementation of Shabal. Cryptology ePrint Archive, Report 2010/292 (2010) Estibals, N.: Compact hardware for computing the Tate pairing over 128-bit-security supersingular curves. In: Joye, M., Miyaji, A., Otsuka, A. (eds.) Pairing-Based Cryptography—Pairing 2010. Lecture Notes in Computer Science. Springer, New York (2010, to appear) Baldwin, B., Byrne, A., Hamilton, M., Hanley, N., McEvoy, R.P., Pan, W., Marnane, W.P.: FPGA implementations of SHA-3 candidates: CubeHash, Grøstl, LANE, Shabal and Spectral Hash. Cryptology ePrint Archive, Report 2009/342 (2009) Helion Technology: FULL DATASHEET—Tiny hash core family for Xilinx FPGA. Revision 2.0 (11 July 2010) Homsirikamol, E., Rogawski, M., Gaj, K.: Comparing hardware performance of fourteen round two SHA-3 candidates using FPGAs. Cryptology ePrint Archive, Report 2010/445 (2010) Bertoni, G., Daemen, J., Peeters, M., Van Assche, G.: Keccak sponge function family main document (version 2.0). http://keccak.noekeon.org (2009) Gauravaram, P., Knudsen, L.R., Matusiewicz, K., Mendel, F., Rechberger, C., Schläffer, M., Thomsen, S.S.: Grøstl—a SHA-3 candidate. http://www.groestl.info (2008) Beuchat, J.-L., Okamoto, E., Yamazaki, T.: Compact implementations of BLAKE-32 and BLAKE-64 on FPGA. In: Bian, J., Zhou, Q., Zhao, K. (eds.) Proceedings of the 2010 International Conference on Field-Programmable Technology—FPT 2010, pp. 170–177. IEEE Press (2010) Bresson, E., Canteaut, A., Chevallier-Mames, B., Clavier, C., Fuhr, T., Gouget, A., Icart, T., Misarsky, J.F., Naya-Plasencia, M., Paillier, P., Pornin, T., Reinhard, J.R., Thuillet, C., Videau, M.: Shabal, a submission to NIST’s cryptographic hash algorithm competition. http://www.shabal.com (2008) Helion Technology: OVERVIEW DATASHEET—Ultra-low resource AES (Rijndael) cores for Xilinx FPGA. Revision 1.3.0 Beuchat, J.-L., Okamoto, E., Yamazaki, T.: A compact FPGA implementation of the SHA-3 candidate ECHO. Cryptology ePrint Archive, Report 2010/364 (2010) Zhai, J., Park, C.M., Wang, G.-N.: Hash-based RFID security protocol using randomly key-changed identification procedure. In: Gavrilova, M., Gervasi, O., Kumar, V., Kenneth Tan, C.J., Taniar, D., Laganà, A., Mun, Y., Choo, H. (eds.) Computational Science and its Applications—ICCSA 2006. Lecture Notes in Computer Science, vol. 3983, pp. 296–305. Springer, New York (2006) GoodT.BenaissaM.Very small FPGA application-specific instruction processor for AESIEEE Trans. Circuits Syst. I: Regular Papers20065371477148610.1109/TCSI.2006.875179 T. Good (9_CR23) 2006; 53 9_CR18 9_CR19 9_CR16 9_CR17 9_CR14 9_CR15 9_CR12 9_CR10 9_CR11 9_CR30 9_CR4 9_CR3 9_CR2 9_CR1 K. Gaj (9_CR20) 2009 9_CR29 9_CR27 9_CR28 9_CR25 9_CR26 J. Daemen (9_CR13) 2002 9_CR24 9_CR21 9_CR9 9_CR22 9_CR8 9_CR7 9_CR6 9_CR5 |
| References_xml | – reference: Boneh, D., Lynn, B., Shacham, H.: Short signatures from the Weil pairing. In: Boyd, C. (ed.) Advances in Cryptology—ASIACRYPT 2001. Lecture Notes in Computer Science, vol. 2248, pp. 514–532. Springer, New York (2001) – reference: Wolkerstorfer, J.: An ASIC implementation of the AES-MixColumn operation. In: Rössler, P., Döderlein, A. (eds.) Proceedings of Austrochip 2001, pp. 129–132 (2001) – reference: Beuchat, J.-L., Okamoto, E., Yamazaki, T.: Compact implementations of BLAKE-32 and BLAKE-64 on FPGA. In: Bian, J., Zhou, Q., Zhao, K. (eds.) Proceedings of the 2010 International Conference on Field-Programmable Technology—FPT 2010, pp. 170–177. IEEE Press (2010) – reference: GoodT.BenaissaM.Very small FPGA application-specific instruction processor for AESIEEE Trans. Circuits Syst. I: Regular Papers20065371477148610.1109/TCSI.2006.875179 – reference: Feron, R., Francq, J.: FPGA implementation of Shabal: Our first results. http://www.shabal.com (2010) – reference: Helion Technology: OVERVIEW DATASHEET—Ultra-low resource AES (Rijndael) cores for Xilinx FPGA. Revision 1.3.0 – reference: Bertoni, G., Daemen, J., Peeters, M., Van Assche, G.: Keccak sponge function family main document (version 2.0). http://keccak.noekeon.org (2009) – reference: Helion Technology: FULL DATASHEET—Tiny hash core family for Xilinx FPGA. Revision 2.0 (11 July 2010) – reference: Good, T., Benaissa, M.: AES on FPGA from the fastest to the smallest. In: Rao, J.R., Sunar, B. (eds.) Cryptographic Hardware and Embedded Systems—CHES 2005. Lecture Notes in Computer Science, vol. 3659, pp. 427–440. Springer, New York (2005) – reference: Beuchat, J.-L., Okamoto, E., Yamazaki, T.: A compact FPGA implementation of the SHA-3 candidate ECHO. Cryptology ePrint Archive, Report 2010/364 (2010) – reference: Zhai, J., Park, C.M., Wang, G.-N.: Hash-based RFID security protocol using randomly key-changed identification procedure. In: Gavrilova, M., Gervasi, O., Kumar, V., Kenneth Tan, C.J., Taniar, D., Laganà, A., Mun, Y., Choo, H. (eds.) Computational Science and its Applications—ICCSA 2006. Lecture Notes in Computer Science, vol. 3983, pp. 296–305. Springer, New York (2006) – reference: Benadjila, R., Billet, O., Gueron, S., Robshaw, M.J.B.: The Intel AES instructions set and the SHA-3 candidates. In: Matsui, M. (ed.) Advances in Cryptology—ASIACRYPT 2009. Lecture Notes in Computer Science, vol. 5912, pp. 162–178. Springer, New York (2009) – reference: Benadjila, R., Billet, O., Gilbert, H., Macario-Rat, G., Peyrin, T., Robshaw, M., Seurin, Y.: SHA-3 proposal: ECHO. http://crypto.rd.francetelecom.com/echo (2009) – reference: Aumasson, J.-P., Henzen, L., Meier, W., Phan, R.C.-W.: SHA-3 proposal BLAKE (version 1.3). http://www.131002.net/blake (2009) – reference: Baldwin, B., Byrne, A., Lu, L., Hamilton, M., Hanley, N., O’Neill, N., Marnane, W.P.: A hardware wrapper for the SHA-3 hash algorithms. Cryptology ePrint Archive, Report 2010/124 (2010) – reference: Feldhofer, M., Dominikus, S., Wolkerstorfer, J.: Strong authentication for RFID systems using the AES algorithm. In: Joye, M., Quisquater, J.-J. (eds.) Cryptographic Hardware and Embedded Systems—CHES 2004. Lecture Notes in Computer Science, vol. 3156, pp. 357–370. Springer, New York (2004) – reference: DaemenJ.RijmenV.The Design of Rijndael2002New YorkSpringer1065.94005 – reference: Gauravaram, P., Knudsen, L.R., Matusiewicz, K., Mendel, F., Rechberger, C., Schläffer, M., Thomsen, S.S.: Grøstl—a SHA-3 candidate. http://www.groestl.info (2008) – reference: Aranha, D.F., Beuchat, J.-L., Detrey, J., Estibals, N.: Optimal Eta pairing on supersingular genus-2 binary hyperelliptic curves. Cryptology ePrint Archive, Report 2010/559 (2010) – reference: Baldwin, B., Byrne, A., Hamilton, M., Hanley, N., McEvoy, R.P., Pan, W., Marnane, W.P.: FPGA implementations of SHA-3 candidates: CubeHash, Grøstl, LANE, Shabal and Spectral Hash. Cryptology ePrint Archive, Report 2009/342 (2009) – reference: GajK.ChodowiecP.KocÇ.K.FPGA and ASIC implementations of the AESCryptographic Engineering2009New YorkSpringer23529410.1007/978-0-387-71817-0_10 – reference: Detrey, J., Gaudry, P., Khalfallah, K.: A low-area yet performant FPGA implementation of Shabal. Cryptology ePrint Archive, Report 2010/292 (2010) – reference: Estibals, N.: Compact hardware for computing the Tate pairing over 128-bit-security supersingular curves. In: Joye, M., Miyaji, A., Otsuka, A. (eds.) Pairing-Based Cryptography—Pairing 2010. Lecture Notes in Computer Science. Springer, New York (2010, to appear) – reference: Järvinen, K.: Sharing resources between AES and the SHA-3 second round candidates Fugue and Grøstl. In: The Second SHA-3 Candidate Conference (2010) – reference: Homsirikamol, E., Rogawski, M., Gaj, K.: Comparing hardware performance of fourteen round two SHA-3 candidates using FPGAs. Cryptology ePrint Archive, Report 2010/445 (2010) – reference: Hämäläinen, P., Alho, T., Hännikäinen, M., Hämäläinen, T.D.: Design and implementation of low-area and low-power AES encryption hardware core. In: Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools—DSD’06, pp. 577–583. IEEE Computer Society (2006) – reference: Bresson, E., Canteaut, A., Chevallier-Mames, B., Clavier, C., Fuhr, T., Gouget, A., Icart, T., Misarsky, J.F., Naya-Plasencia, M., Paillier, P., Pornin, T., Reinhard, J.R., Thuillet, C., Videau, M.: Shabal, a submission to NIST’s cryptographic hash algorithm competition. http://www.shabal.com (2008) – reference: Bulens, P., Standaert, F.-X., Quisquater, J.-J., Pellegrin, P., Rouvroy, G.: Implementation of the AES-128 on Virtex-5 FPGAs. In: Vaudenay, S. (ed.) Progress in Cryptology—AFRICACRYPT 2008. Lecture Notes in Computer Science, vol. 5023, pp. 16–26. Springer, New York (2008) – reference: El-Hadedy, M., Gligoroski, D., Knapskog, S.J.: Single core implementation of Blue Midnight Wish hash function on VIRTEX 5 platform. http://tinyurl.com/3xhvx6c (2010) – reference: El-Hadedy, M., Margala, M., Gligoroski, D., Knapskog, S.J.: Resource-efficient implementation of Blue Midnight Wish-256 hash function on Xilinx FPGA platform. In: The Second SHA-3 Candidate Conference, August 2010 – ident: 9_CR6 doi: 10.1007/978-3-642-10366-7_10 – ident: 9_CR7 – ident: 9_CR11 – ident: 9_CR4 doi: 10.1049/cp.2010.0478 – ident: 9_CR24 doi: 10.1109/DSD.2006.40 – ident: 9_CR15 doi: 10.1109/ReConFig.2010.44 – start-page: 235 volume-title: Cryptographic Engineering year: 2009 ident: 9_CR20 doi: 10.1007/978-0-387-71817-0_10 – ident: 9_CR30 doi: 10.1007/11751632_32 – ident: 9_CR18 doi: 10.1007/978-3-540-28632-5_26 – ident: 9_CR1 – ident: 9_CR9 doi: 10.1109/FPT.2010.5681776 – ident: 9_CR26 – ident: 9_CR5 – ident: 9_CR28 – ident: 9_CR10 doi: 10.1007/3-540-45682-1_30 – ident: 9_CR8 – ident: 9_CR17 doi: 10.1007/978-3-642-17455-1_25 – ident: 9_CR16 doi: 10.1109/ISIAS.2010.5604066 – ident: 9_CR12 doi: 10.1007/978-3-540-68164-9_2 – ident: 9_CR14 doi: 10.1007/978-3-642-19574-7_7 – ident: 9_CR19 – ident: 9_CR21 – ident: 9_CR2 – ident: 9_CR3 doi: 10.1109/DSD.2009.162 – volume: 53 start-page: 1477 issue: 7 year: 2006 ident: 9_CR23 publication-title: IEEE Trans. Circuits Syst. I: Regular Papers doi: 10.1109/TCSI.2006.875179 – ident: 9_CR25 – volume-title: The Design of Rijndael year: 2002 ident: 9_CR13 doi: 10.1007/978-3-662-04722-4 – ident: 9_CR22 doi: 10.1007/11545262_31 – ident: 9_CR27 – ident: 9_CR29 |
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| Title | A low-area unified hardware architecture for the AES and the cryptographic hash function ECHO |
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