Analysis and Implementation of Multiple-Input, Multiple-Output VBLAST Receiver From Area and Power Efficiency Perspective
This paper presents an analysis of the vertical Bell Laboratories layered space time (VBLAST) receiver used in a multiple-input multiple-output (MIMO) wireless system from the hardware implementation perspective and identifies those processing elements that consume more area and power due to complex...
Uložené v:
| Vydané v: | IEEE transactions on very large scale integration (VLSI) systems Ročník 14; číslo 11; s. 1281 - 1286 |
|---|---|
| Hlavní autori: | , , , |
| Médium: | Journal Article |
| Jazyk: | English |
| Vydavateľské údaje: |
Piscataway, NJ
IEEE
01.11.2006
Institute of Electrical and Electronics Engineers The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Predmet: | |
| ISSN: | 1063-8210, 1557-9999 |
| On-line prístup: | Získať plný text |
| Tagy: |
Pridať tag
Žiadne tagy, Buďte prvý, kto otaguje tento záznam!
|
| Abstract | This paper presents an analysis of the vertical Bell Laboratories layered space time (VBLAST) receiver used in a multiple-input multiple-output (MIMO) wireless system from the hardware implementation perspective and identifies those processing elements that consume more area and power due to complex signal processing. This paper models a scalable VBLAST receiver based on minimum mean square error (MMSE) nulling criteria assuming a block flat fading channel. After identifying the major area and power consuming blocks, this paper proposes two area and power efficient VLSI architectures for the block that computes pseudoinverse of the channel matrix. This paper discusses different tradeoff issues in both architectures and compares them with the architectures in the literature |
|---|---|
| AbstractList | This paper presents an analysis of the vertical Bell Laboratories layered space time (VBLAST) receiver used in a multiple-input multiple-output (MIMO) wireless system from the hardware implementation perspective and identifies those processing elements that consume more area and power due to complex signal processing. This paper models a scalable VBLAST receiver based on minimum mean square error (MMSE) nulling criteria assuming a block flat fading channel. After identifying the major area and power consuming blocks, this paper proposes two area and power efficient VLSI architectures for the block that computes pseudoinverse of the channel matrix. This paper discusses different tradeoff issues in both architectures and compares them with the architectures in the literature |
| Author | Khan, Z. Arslan, T. Thompson, J.S. Erdogan, A.T. |
| Author_xml | – sequence: 1 givenname: Z. surname: Khan fullname: Khan, Z. organization: Sch. of Eng. & Electron., Univ. of Edinburgh – sequence: 2 givenname: T. surname: Arslan fullname: Arslan, T. organization: Sch. of Eng. & Electron., Univ. of Edinburgh – sequence: 3 givenname: J.S. surname: Thompson fullname: Thompson, J.S. organization: Sch. of Eng. & Electron., Univ. of Edinburgh – sequence: 4 givenname: A.T. surname: Erdogan fullname: Erdogan, A.T. organization: Sch. of Eng. & Electron., Univ. of Edinburgh |
| BackLink | http://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=18344599$$DView record in Pascal Francis |
| BookMark | eNp9kUtr3DAUhUVIIY_2B4RuTKF0U0-vZPmh5TQk7cCUhGaSrVCkK1CwZVeSW-bfV4lDCln0bnR1-M5Z3HNCDv3okZAzCitKQXzZ3W1vNisG0Ky6ruFQHZBjWtdtKfIc5h2aquwYhSNyEuMDAOVcwDHZr73q99HFQnlTbIapxwF9UsmNvhht8WPuk8tiufHTnD7_-1_NKQvF3dft-mZX_ESN7jeG4jKMQ7EOqJ7yrsc_Wbuw1mmHXu-LawxxQp0y-5a8saqP-O75PSW3lxe78-_l9urb5ny9LXVV81QyrTQ1LbQtM61l1N4za5VhCpQxRumWMWE7Ud8bWzcGGCCwiqnWIhPIFatOyacldwrjrxljkoOLGvteeRznKLtOcBA16zL54RX5MM4h3ydKQRmDjrVVhj4-Qypq1dugvHZRTsENKuwl7SrOayEy1y6cDmOMAa3UbjlrCsr1koJ8LE4-FScfi5NLcdlJXzlfwv_jeb94HCK-8Byo4A2t_gLXHqci |
| CODEN | IEVSE9 |
| CitedBy_id | crossref_primary_10_1109_TCSI_2009_2037391 crossref_primary_10_1109_TCSI_2009_2025803 |
| Cites_doi | 10.1109/ICASSP.2000.859065 10.1109/ISSSE.1998.738086 10.1109/PIMRC.2003.1259266 10.1109/79.526897 10.1109/ISVLSI.2006.41 10.1109/WCNC.2005.1424535 10.1002/bltj.2015 10.1109/JSSC.2004.831454 10.1109/ISCAS.1992.230297 10.1109/JSAC.2003.809724 |
| ContentType | Journal Article |
| Copyright | 2007 INIST-CNRS Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2006 |
| Copyright_xml | – notice: 2007 INIST-CNRS – notice: Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2006 |
| DBID | 97E RIA RIE AAYXX CITATION IQODW 7SP 8FD L7M F28 FR3 |
| DOI | 10.1109/TVLSI.2006.886403 |
| DatabaseName | IEEE All-Society Periodicals Package (ASPP) 2005–Present IEEE All-Society Periodicals Package (ASPP) 1998–Present IEEE/IET Electronic Library (IEL) (UW System Shared) CrossRef Pascal-Francis Electronics & Communications Abstracts Technology Research Database Advanced Technologies Database with Aerospace ANTE: Abstracts in New Technology & Engineering Engineering Research Database |
| DatabaseTitle | CrossRef Technology Research Database Advanced Technologies Database with Aerospace Electronics & Communications Abstracts Engineering Research Database ANTE: Abstracts in New Technology & Engineering |
| DatabaseTitleList | Engineering Research Database |
| Database_xml | – sequence: 1 dbid: RIE name: IEL url: https://ieeexplore.ieee.org/ sourceTypes: Publisher |
| DeliveryMethod | fulltext_linktorsrc |
| Discipline | Engineering Applied Sciences Architecture |
| EISSN | 1557-9999 |
| EndPage | 1286 |
| ExternalDocumentID | 2544646401 18344599 10_1109_TVLSI_2006_886403 4019461 |
| Genre | orig-research |
| GroupedDBID | -~X .DC 0R~ 29I 3EH 4.4 5GY 5VS 6IK 97E AAJGR AARMG AASAJ AAWTH ABAZT ABFSI ABQJQ ABVLG ACGFS ACIWK AENEX AETIX AGQYO AGSQL AHBIQ AI. AIBXA AKJIK AKQYR ALLEH ALMA_UNASSIGNED_HOLDINGS ATWAV BEFXN BFFAM BGNUA BKEBE BPEOZ CS3 DU5 E.L EBS EJD HZ~ H~9 ICLAB IEDLZ IFIPE IFJZH IPLJI JAVBF LAI M43 O9- OCL P2P RIA RIE RNS TN5 VH1 AAYXX CITATION IQODW RIG 7SP 8FD L7M F28 FR3 |
| ID | FETCH-LOGICAL-c354t-2cac1d70772d7f21fb2ffad2a0adddac7229f895bdf56d020e0232a7fe29e4a23 |
| IEDL.DBID | RIE |
| ISICitedReferencesCount | 2 |
| ISICitedReferencesURI | http://www.webofscience.com/api/gateway?GWVersion=2&SrcApp=Summon&SrcAuth=ProQuest&DestLinkType=CitingArticles&DestApp=WOS_CPL&KeyUT=000242554900011&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D |
| ISSN | 1063-8210 |
| IngestDate | Thu Oct 02 05:16:56 EDT 2025 Sun Nov 30 04:39:36 EST 2025 Mon Jul 21 09:13:24 EDT 2025 Sat Nov 29 03:35:59 EST 2025 Tue Nov 18 22:21:57 EST 2025 Tue Aug 26 16:37:58 EDT 2025 |
| IsPeerReviewed | true |
| IsScholarly | true |
| Issue | 11 |
| Keywords | Performance evaluation Fading MIMO system minimum mean square error (MMSE) VLSI circuit Processor Scalability Square root VLSI multiple-input multiple-output (MIMO) wireless system Index Terms-CORDIC Receiver pseudoinverse Space time Algorithm Implementation Mean square error Jacobi rotation Circuit architecture square root algorithm Integrated circuit Signal processing vertical Bell Laboratories layered space time (VBLAST) |
| Language | English |
| License | https://ieeexplore.ieee.org/Xplorehelp/downloads/license-information/IEEE.html CC BY 4.0 |
| LinkModel | DirectLink |
| MergedId | FETCHMERGED-LOGICAL-c354t-2cac1d70772d7f21fb2ffad2a0adddac7229f895bdf56d020e0232a7fe29e4a23 |
| Notes | ObjectType-Article-2 SourceType-Scholarly Journals-1 ObjectType-Feature-1 content type line 14 content type line 23 |
| PQID | 912208273 |
| PQPubID | 85424 |
| PageCount | 6 |
| ParticipantIDs | proquest_journals_912208273 ieee_primary_4019461 pascalfrancis_primary_18344599 crossref_citationtrail_10_1109_TVLSI_2006_886403 proquest_miscellaneous_889409528 crossref_primary_10_1109_TVLSI_2006_886403 |
| PublicationCentury | 2000 |
| PublicationDate | 2006-11-01 |
| PublicationDateYYYYMMDD | 2006-11-01 |
| PublicationDate_xml | – month: 11 year: 2006 text: 2006-11-01 day: 01 |
| PublicationDecade | 2000 |
| PublicationPlace | Piscataway, NJ |
| PublicationPlace_xml | – name: Piscataway, NJ – name: New York |
| PublicationTitle | IEEE transactions on very large scale integration (VLSI) systems |
| PublicationTitleAbbrev | TVLSI |
| PublicationYear | 2006 |
| Publisher | IEEE Institute of Electrical and Electronics Engineers The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher_xml | – name: IEEE – name: Institute of Electrical and Electronics Engineers – name: The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| References | ref8 ref7 golub (ref6) 1996 ref9 ref4 ref3 ref11 ref10 ref5 ref2 ref1 |
| References_xml | – ident: ref7 doi: 10.1109/ICASSP.2000.859065 – ident: ref4 doi: 10.1109/ISSSE.1998.738086 – ident: ref8 doi: 10.1109/PIMRC.2003.1259266 – ident: ref11 doi: 10.1109/79.526897 – ident: ref9 doi: 10.1109/ISVLSI.2006.41 – ident: ref5 doi: 10.1109/WCNC.2005.1424535 – ident: ref1 doi: 10.1002/bltj.2015 – ident: ref3 doi: 10.1109/JSSC.2004.831454 – ident: ref10 doi: 10.1109/ISCAS.1992.230297 – year: 1996 ident: ref6 publication-title: Matrix Computation – ident: ref2 doi: 10.1109/JSAC.2003.809724 |
| SSID | ssj0014490 |
| Score | 1.8018486 |
| Snippet | This paper presents an analysis of the vertical Bell Laboratories layered space time (VBLAST) receiver used in a multiple-input multiple-output (MIMO) wireless... |
| SourceID | proquest pascalfrancis crossref ieee |
| SourceType | Aggregation Database Index Database Enrichment Source Publisher |
| StartPage | 1281 |
| SubjectTerms | Applied sciences Architecture Bit error rate Blocking Channels Computational complexity Computer architecture CORDIC Design. Technologies. Operation analysis. Testing Electronics Exact sciences and technology Hardware Integrated circuits Integrated circuits by function (including memories and processors) Jacobi rotation Mathematical models Mean square error methods MIMO minimum mean square error (MMSE) multiple-input multiple-output (MIMO) wireless system Nulling Power system modeling pseudoinverse Receivers Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Signal processing algorithms square root algorithm Transmitting antennas vertical Bell Laboratories layered space time (VBLAST) Very large scale integration VLSI |
| Title | Analysis and Implementation of Multiple-Input, Multiple-Output VBLAST Receiver From Area and Power Efficiency Perspective |
| URI | https://ieeexplore.ieee.org/document/4019461 https://www.proquest.com/docview/912208273 https://www.proquest.com/docview/889409528 |
| Volume | 14 |
| WOSCitedRecordID | wos000242554900011&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D |
| hasFullText | 1 |
| inHoldings | 1 |
| isFullTextHit | |
| isPrint | |
| journalDatabaseRights | – providerCode: PRVIEE databaseName: IEL customDbUrl: eissn: 1557-9999 dateEnd: 99991231 omitProxy: false ssIdentifier: ssj0014490 issn: 1063-8210 databaseCode: RIE dateStart: 19930101 isFulltext: true titleUrlDefault: https://ieeexplore.ieee.org/ providerName: IEEE |
| link | http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV1Lb9QwELZKxQEOvApiW6h84IRqmjhObB8L6opKpazUpeotmvghVaJJtZsg9d8zdrxZEAiJWx6OHeWzMzOex0fIuxKcRckGTCoAJpwzDMDnLG8qLhxaPpCbSDYhLy7U9bVe7JCjKRfGOReDz9yHcBh9-bYzQ9gqO0ZbQItg6zyQshpztSaPgRB6rDxQFUyhHZM8mHmmj5dX55dno99BqUps-LGSDIqkKiEkEtb4VfxIZ_HHnzmKm_nT_3vRZ-RJUivpyTgPnpMd174gj38pNrhH7jf1Ryi0lsaqwLcp8ailnadfUmghO2vvhv5oe_516PECvfp4fnK5pKhnuhDLQeer7hYHdBD7WwS2NXoaC1KEbE662GZxviTf5qfLT59ZIl5gpihFz7gBk1uZoeZtpee5b7j3YDlk-De0YCTn2itdNtaXlUWF06Hk5yC949oJ4MUrstt2rXtNqPEOFZZCi8IjQg2AUk2lTFkVwSGa8RnJNlDUJlUlD-QY3-tonWS6jugFtsyqHtGbkffTI3djSY5_Nd4L8EwNEzIzcvgb3tuOAu9IqfWMHGwmQJ1W9brWOeeoMknslU53cTkGHwu0rhvWOKpGi7nkav_vAx-QR3ETJ2YzviG7_Wpwb8lD86O_Wa8O45T-Cc3K9dc |
| linkProvider | IEEE |
| linkToHtml | http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV1Lb9QwELaqggQceBXEUig-cEI1TRwnsY8FddUV22WlLlVv0cQPCYkm1W6CxL9n7HizIBAStzwcO8pnZ2Y8j4-QtzlYg5INWCkBmLBWMwCXsrQuuLBo-UCqA9lEuVjI62u13CPHYy6MtTYEn9n3_jD48k2re79VdoK2gBLe1rmTC8GTIVtr9BkIoYbaA0XGJFoy0YeZJupkdTW_nA2eBykLsWXIilIo0Kr4oEjY4HdxA6HFH__mIHCmj_7vVR-Th1GxpKfDTHhC9mzzlDz4pdzgAfmxrUBCoTE01AW-ialHDW0dvYjBhWzW3Pbd8e78c9_hBXr1YX56uaKoaVofzUGn6_YGB7QQ-lt6vjV6FkpS-HxOutzlcT4jX6Znq4_nLFIvMJ3lomNcg05NmaDubUrHU1dz58BwSPB_aECXnCsnVV4blxcGVU6Lsp9D6SxXVgDPnpP9pm3sC0K1s6iyZEpkDhGqAaSsC6nzIvMu0YRPSLKFotKxLrmnx_hWBfskUVVAz_NlFtWA3oS8Gx-5HYpy_KvxgYdnbBiRmZCj3_DedeSZR3KlJuRwOwGquK43lUo5R6WpxF7peBcXpPeyQGPbfoOjKrSZcy5f_n3gN-Te-epiXs1ni0-H5H7Y0gm5ja_Ifrfu7WtyV3_vvm7WR2F6_wS24vke |
| openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.atitle=Analysis+and+Implementation+of+Multiple%E2%80%93Input%2C+Multiple%E2%80%93Output+VBLAST+Receiver+From+Area+and+Power+Efficiency+Perspective&rft.jtitle=IEEE+transactions+on+very+large+scale+integration+%28VLSI%29+systems&rft.au=Khan%2C+Zahid&rft.au=Arslan%2C+Tughrul&rft.au=Thompson%2C+John+S.&rft.au=Erdogan%2C+Ahmet+T.&rft.date=2006-11-01&rft.issn=1063-8210&rft.volume=14&rft.issue=11&rft.spage=1281&rft.epage=1286&rft_id=info:doi/10.1109%2FTVLSI.2006.886403&rft.externalDBID=n%2Fa&rft.externalDocID=10_1109_TVLSI_2006_886403 |
| thumbnail_l | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/lc.gif&issn=1063-8210&client=summon |
| thumbnail_m | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/mc.gif&issn=1063-8210&client=summon |
| thumbnail_s | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/sc.gif&issn=1063-8210&client=summon |