FPGA implementation of HOOFR bucketing extractor-based real-time embedded SLAM applications

Feature extraction is an important vision task in many applications like simultaneous localization and mapping (SLAM). In the recent computing systems, FPGA-based acceleration have presented a strong competition to GPU-based acceleration due to its high computation capabilities and lower energy cons...

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Vydané v:	Journal of real-time image processing Ročník 18; číslo 3; s. 525 - 538
Hlavní autori:	Nguyen, Dai Duong, El Ouardi, Abdelhafid, Rodriguez, Sergio, Bouaziz, Samir
Médium:	Journal Article
Jazyk:	English
Vydavateľské údaje:	Berlin/Heidelberg Springer Berlin Heidelberg 01.06.2021 Springer Nature B.V Springer Verlag
Predmet:	Algorithms Computation Computer Graphics Computer Science Design Designers Eigenvalues Energy consumption Feature extraction Field programmable gate arrays High level synthesis Image Processing and Computer Vision Memory Multimedia Information Systems Neural networks Original Research Paper Pattern Recognition Pixels Robotics Signal,Image and Speech Processing Simultaneous localization and mapping System on chip FPGA implementation Embedded systems Features extraction Parallel image processing
ISSN:	1861-8200, 1861-8219
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Abstract	Feature extraction is an important vision task in many applications like simultaneous localization and mapping (SLAM). In the recent computing systems, FPGA-based acceleration have presented a strong competition to GPU-based acceleration due to its high computation capabilities and lower energy consumption. In this paper, we present a high-level synthesis implementation on a SoC-FPGA of a feature extraction algorithm dedicated for SLAM applications. We choose HOOFR extraction algorithm which provides a robust performance but requires a significant computation on embedded CPU. Our system is dedicated for SLAM applications so that we also integrated bucketing detection method in order to have a homogeneous distribution of keypoints in the image. Moreover, instead of optimizing performance by simplifying the original algorithm as in many other researches, we respected the complexity of HOOFR extractor and have parallelized the processing operations. The design has been validated on an Intel Arria 10 SoC-FPGA with a throughput of 54 fps at 1226 × 370 pixels (handling 1750 features) or 14 fps at 1920 × 1080 pixels (handling 6929 features).
AbstractList	Feature extraction is an important vision task in many applications like simultaneous localization and mapping (SLAM). In the recent computing systems, FPGA-based acceleration have presented a strong competition to GPU-based acceleration due to its high computation capabilities and lower energy consumption. In this paper, we present a high-level synthesis implementation on a SoC-FPGA of a feature extraction algorithm dedicated for SLAM applications. We choose HOOFR extraction algorithm which provides a robust performance but requires a significant computation on embedded CPU. Our system is dedicated for SLAM applications so that we also integrated bucketing detection method in order to have a homogeneous distribution of keypoints in the image. Moreover, instead of optimizing performance by simplifying the original algorithm as in many other researches, we respected the complexity of HOOFR extractor and have parallelized the processing operations. The design has been validated on an Intel Arria 10 SoC-FPGA with a throughput of 54 fps at 1226×370 pixels (handling 1750 features) or 14 fps at 1920×1080 pixels (handling 6929 features). Feature extraction is an important vision task in many applications like simultaneous localization and mapping (SLAM). In the recent computing systems, FPGA-based acceleration have presented a strong competition to GPU-based acceleration due to its high computation capabilities and lower energy consumption. In this paper, we present a high-level synthesis implementation on a SoC-FPGA of a feature extraction algorithm dedicated for SLAM applications. We choose HOOFR extraction algorithm which provides a robust performance but requires a significant computation on embedded CPU. Our system is dedicated for SLAM applications so that we also integrated bucketing detection method in order to have a homogeneous distribution of keypoints in the image. Moreover, instead of optimizing performance by simplifying the original algorithm as in many other researches, we respected the complexity of HOOFR extractor and have parallelized the processing operations. The design has been validated on an Intel Arria 10 SoC-FPGA with a throughput of 54 fps at 1226 × 370 pixels (handling 1750 features) or 14 fps at 1920 × 1080 pixels (handling 6929 features).
Author	Bouaziz, Samir El Ouardi, Abdelhafid Rodriguez, Sergio Nguyen, Dai Duong
Author_xml	– sequence: 1 givenname: Dai Duong surname: Nguyen fullname: Nguyen, Dai Duong organization: School of Electrical Engineering, Hanoi University of Science and Technology – sequence: 2 givenname: Abdelhafid orcidid: 0000-0003-3665-2185 surname: El Ouardi fullname: El Ouardi, Abdelhafid email: abdelhafid.elouardi@universite-paris-saclay.fr organization: Systèmes et Applications des Technologies de l’Information et de l’Energie, CNRS, ENS Paris-Saclay, Université Paris-Saclay – sequence: 3 givenname: Sergio surname: Rodriguez fullname: Rodriguez, Sergio organization: Systèmes et Applications des Technologies de l’Information et de l’Energie, CNRS, ENS Paris-Saclay, Université Paris-Saclay – sequence: 4 givenname: Samir surname: Bouaziz fullname: Bouaziz, Samir organization: Systèmes et Applications des Technologies de l’Information et de l’Energie, CNRS, ENS Paris-Saclay, Université Paris-Saclay
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Copyright	Springer-Verlag GmbH Germany, part of Springer Nature 2020 Springer-Verlag GmbH Germany, part of Springer Nature 2020. Distributed under a Creative Commons Attribution 4.0 International License
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SubjectTerms	Algorithms Computation Computer Graphics Computer Science Design Designers Eigenvalues Energy consumption Feature extraction Field programmable gate arrays High level synthesis Image Processing and Computer Vision Memory Multimedia Information Systems Neural networks Original Research Paper Pattern Recognition Pixels Robotics Signal,Image and Speech Processing Simultaneous localization and mapping System on chip
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Title	FPGA implementation of HOOFR bucketing extractor-based real-time embedded SLAM applications
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